Resistive Memory Cell Parallel Merging for Sense Margin
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Solution Overview
Problem
Resistive memory devices face challenges in maintaining a sufficient sense margin due to variations in resistance values during fabrication and over time, leading to reduced read data accuracy and performance, especially when using existing DRAM fabrication processes.
Innovation Solution
Implementing a memory cell parallel merging scheme where two or more resistive memory cells are operated in parallel to increase the sense margin by reducing effective resistance and doubling the current difference between high and low logical states, thereby ensuring accurate detection of logical states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing DRAM fabrication processes are used for resistive memory, then manufacturing compatibility is improved, but resistance value variation and sense margin are worsened
Solution Approach 1:
The patent merges multiple resistive memory cells in parallel to form a composite cell. By combining N cells (where N≥2), the effective resistance is reduced and the sense margin is increased. This merging approach compensates for the resistance value variations caused by using existing DRAM fabrication processes, thereby resolving the contradiction between manufacturing compatibility and manufacturing precision.
2Ease of manufacture
If resistance values are distributed over a range due to fabrication limitations, then manufacturing ease is improved, but measurement precision and sense margin are worsened
Solution Approach 1:
By merging N resistive memory cells in parallel, the patent creates a composite cell with reduced effective resistance and enhanced sense margin. The combined current from multiple cells amplifies the signal difference between logical states, thereby improving measurement precision despite the resistance distribution caused by fabrication flexibility.
Solution Approach 2:
The patent uses multiple copies of the same memory cell structure in parallel. By replicating the cell design N times and operating them in parallel, the system achieves better signal differentiation and sense margin without requiring more complex individual cell designs, thus maintaining fabrication ease while improving measurement precision.
3Duration of action of stationary object
If resistance values vary over time, then long-term operation is affected, but data retention and reliability are worsened
Solution Approach 1:
The patent merges multiple memory cells in parallel to create a more robust composite cell. The combined current signal from N cells provides a larger margin for detecting logical states, which compensates for resistance variations that occur over time. This enhances reliability and data retention during long-term operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The memory cell parallel merging scheme effectively doubles the sense margin, enhancing read accuracy and operational characteristics of resistive memory devices, even when fabricated using existing DRAM processes, by increasing the current difference between reset and set states, thus improving data retention and error rates.
Implementation Method 1
a variable resistance element whose resistance value can change between a low level and a high level
Implementation Method 2
two or more resistive memory cells are operated in parallel to increase the sense margin by reducing effective resistance
Data Source
AI summary
A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.