Phase Change Memory Multiprogramming Voltage Control
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Solution Overview
Problem
Conventional phase change memory devices face issues with undesirably increasing word line voltages due to parasitic resistance and capacitance, which can deteriorate programming characteristics, especially when programming current is applied to multiple memory cells simultaneously.
Innovation Solution
The implementation of a multiprogramming method that limits the number of simultaneously programmed memory cells to prevent voltage increases, using a memory cell array with block units and write driver circuits to provide programming currents to selected memory blocks, and a column selection circuit to manage programming operations, thereby reducing current flow through word lines and minimizing voltage elevation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If programming current is applied to multiple memory cells simultaneously, then programming speed is improved, but word line voltage increases due to parasitic resistance and capacitance
Solution Approach 1:
The memory cell array is divided into multiple block units, each connected to a separate write driver unit. This segmentation allows programming operations to be performed on smaller groups of memory cells simultaneously, reducing the total current through each word line while maintaining overall programming efficiency. Each block unit can be independently controlled, enabling parallel programming without excessive voltage buildup on individual word lines.
2Productivity
If more memory cells are programmed simultaneously, then throughput is improved, but voltage elevation on word lines increases
Solution Approach 1:
Write driver units serve as intermediary components between the control circuitry and the memory cell array. Each write driver unit manages a specific block unit, acting as a buffer that controls and limits the current flow to prevent excessive voltage elevation on word lines while still enabling efficient programming operations. This intermediary structure allows the system to scale throughput without proportionally increasing harmful voltage effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents voltage level increases on word lines, thereby maintaining stable programming characteristics and improving the reliability of phase change memory devices by subdividing memory cells into smaller groups for separate programming, reducing the impact of parasitic resistances and capacitances.
Implementation Method 1
Phase change memory devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases
Implementation Method 2
The phase change material in a PRAM is converted to the amorphous state by heating the material to above a predetermined melting temperature and then quickly cooling the material
Implementation Method 3
The phase change material is converted to the crystalline state by heating the material at another predetermined temperature below the melting temperature for a period of time
Data Source
AI summary
A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit includes a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.