3D Memory Read Disturb Mitigation via Deck Voltage Control
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Solution Overview
Problem
Three-dimensional memory devices experience read disturb due to varying aperture sizes of channel holes, leading to increased electric field intensity and reduced reliability as the number of stack layers increases, causing errors in data storage.
Innovation Solution
A control method for three-dimensional memory that applies a first pass voltage lower than the normal pass voltage to memory cells with smaller channel structures during read operations, and adjusts voltages based on the states of non-selected memory cells during program verify operations to reduce read disturb and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stack layers is increased to increase integration density, then the storage capacity is improved, but the aperture difference between upper and lower channel holes increases causing higher electric field intensity and read disturb
Solution Approach 1:
The patent divides the memory cells into different groups based on their channel hole aperture sizes. Memory cells with smaller apertures (typically in lower decks) are assigned different read voltages compared to memory cells with larger apertures (typically in upper decks). This local differentiation allows each group to be read with optimized voltage levels, preventing excessive electric field intensity in small-aperture cells while maintaining read capability across all cells.
Solution Approach 2:
The patent changes the read voltage parameter based on the channel hole aperture size and deck position. By implementing multiple read voltage levels (e.g., first read voltage for small-aperture cells, second read voltage for large-aperture cells), the system adapts the electrical parameters to the physical characteristics of different memory cell groups, thereby reducing read disturb in vulnerable cells while maintaining efficient reading in robust cells.
2Ease of operation
If a uniform pass voltage is applied to all memory cells during read operations, then the operation is simple, but memory cells with smaller channel apertures experience higher electric field intensity causing read disturb
Solution Approach 1:
The patent applies different pass voltage levels to different groups of memory cells based on their aperture characteristics. Memory cells with smaller channel apertures receive a first pass voltage level, while memory cells with larger apertures receive a second pass voltage level. This differentiated approach ensures that small-aperture cells are not subjected to excessively high electric fields that would cause read disturb, while large-aperture cells continue to operate efficiently.
Solution Approach 2:
The patent segments the memory cell array into multiple decks or groups based on their vertical position and aperture characteristics. Each segment is then controlled with appropriate voltage levels during read operations. This segmentation allows the system to manage the complexity of differentiated voltage control in an organized manner, applying lower pass voltages to vulnerable lower-deck cells and standard pass voltages to upper-deck cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces read disturb in memory cells with smaller aperture channel structures, enhancing the reliability of three-dimensional memory devices by applying tailored voltages during read and program verify operations.
Implementation Method 1
if the aperture of the channel hole where the memory cells are located is relatively small, then the pass voltage brings higher electric field intensity to the memory cells
Data Source
AI summary
The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage. The first pass voltage is applied to first non-selected memory cells in the first portion, and the second pass voltage is applied to second non-selected memory cells in the second portion.