Read-Only Memories TRIZ Cases

A memory controller selects adaptive read thresholds based on bit errors to manage 3D NAND storage operations.

A row decoder places functionally corresponding transistors in different rows to increase gate width and gap.

Parallel NMOS transistors generate a temperature-compensated reference current, eliminating cell disturb drift from traditional reference cells.

Replacing static primary data caches with a single dynamic latch reduces page buffer area and increases programming speed for multi-level cell memory devices.

Segmenting bitlines resolves conflicts between high-speed reading and high-current writing, reducing peripheral circuit complexity.

A semiconductor memory voltage generator switches bulk voltage sources to reduce power consumption.

Bit-pair trimming data stored in memory cells regulates reference current to resolve deadlock issues without increasing chip area or test cost.

A DDR nonvolatile memory architecture integrates volatile and non-volatile arrays to support high-speed data transfers on both clock edges.

A tri-gate method programs both SONOS transistors in an nvSRAM cell simultaneously through shared word lines and bit lines.

Centralized comparison logic array reduces global address line load, enabling high-speed operation and minimizing chip size.

A non-volatile memory device uses segmented foggy and fine programming operations to adjust threshold voltage levels in storage cells.

Charging selection lines during bit line setup intervals reduces word line charging time without increasing chip area or pump capacity.

Dividing row decoders into upper and lower groups reduces the high voltage generator load to one-eighth, minimizing pumping capacitor size.

A nonvolatile memory device recovers unselected word-line voltage levels using a dedicated discharge circuit.

Separate command and address buses enable configurable-width memory channels that reduce power consumption by activating only necessary memory devices.

A charge trap flash memory device adjusts erase operation parameters based on temperature detection results to ensure stable performance.

Middle-out programming sequences bias the polysilicon channel to remove residual electrons, preventing program disturb and improving data retention.

An anti-ferroelectric threshold switch minimizes residual polarization and leakage currents in memory cells by switching states at specific voltage thresholds.

A memory device integrates OTP and pseudo-MTP blocks using a mark bit storage area to differentiate data states.

A source line voltage adjuster dynamically regulates output current using an operational amplifier and current generator to maintain stable common source line voltages.

Trimmable clamping circuits adjust threshold voltages to match reference cells, reducing offset compensation range and area overhead in non-volatile memory.

Estimating reference voltages from read data to perform initial sector reads and update log-likelihood ratios.

Impurity grading in select transistors reduces leak current from unselected strings while maintaining hole generation for erase operations.

A non-volatile memory controller applies temperature compensation to adjust voltage and timing settings based on operation temperature.

Compensation source adjusts voltage dynamics at sensing node to differentiate cell states when current differences remain minimal.

A page buffer circuit uses tri-state inverters to transmit and restore data via a shared sensing node.

A semiconductor memory device adjusts pass voltage magnitudes based on temperature to maintain read accuracy.

Segmenting a ReRAM array into formed and unformed cells increases the read margin by maintaining a super high resistance state in unformed cells.

Shared level shift circuits reduce transistor count and chip area by merging multiple word line driving functions into universal resources.

A memory controller categorizes flash blocks by program state to select the correct read voltage level.

A page buffer circuit uses a unified register to store higher and lower data bits for flash memory operations.

A flash memory apparatus applies a boost voltage to the source discharge transistor gate during data reading operations.

An adaptive data retention management system adjusts non-volatile memory refresh rates based on temperature monitoring.

A look neighbor ahead pre-read method classifies neighboring word line data states to apply targeted retention compensation schemes.

Vertical conductive layers form stacked capacitors in a booster circuit, reducing peripheral area while maintaining voltage boosting.

A semiconductor memory device uses pass transistors with channel areas sized by voltage range to reduce row decoder footprint.

A non-volatile memory cell couples a two-terminal fuse and three-terminal antifuse in series to enable high-density array integration.

A semiconductor memory device segments cell strings to apply uniform precharge voltages across even and odd bit lines.

Gaussian modeling estimates soft-read thresholds using distinct mean and standard deviation parameters for each cell voltage level distribution.

A semiconductor memory device applies specific voltages to a dummy word line between sub blocks.

A nonvolatile memory device adapts threshold voltage state orders to accelerate read operations during multi-bit programming cycles.

Hot hole injection narrows threshold voltage distributions in nonvolatile memory devices, resolving reliability issues caused by wide voltage spreads.

A nonvolatile memory device executes a data read on victim sub-blocks before erasing a selected block.

Leveraging leakage magnetic fields between densely packed magnetoresistive effect elements enhances data retention while minimizing thermal stability issues.

Differentiated pass voltages applied to 3D memory decks reduce read disturb in small-aperture cells, improving device reliability.

A switch circuit manages energy storage to maintain voltage levels during input fluctuations.

A word-line driver uses a PMOS clamp transistor to pull the output node low during standby mode.

A memory block test method evaluates individual page programming times to allow faster pages to compensate for slower ones during manufacturing.

A mirroring and amplifying unit processes sensing currents from flash memory cells to determine internal circuit states.