Stacked Capacitor Booster Circuit for 3D Memory Area Reduction
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Solution Overview
Problem
Three-dimensional memory cell arrays require significant area for peripheral circuitry, including booster and oscillating circuits, which hinders the miniaturization of semiconductor devices.
Innovation Solution
The semiconductor device incorporates a booster circuit with series-connected rectifier cells and capacitors, where the capacitors are formed between conductive layers stacked perpendicularly to the substrate, reducing the occupied area by utilizing a laminate structure that allows for efficient voltage boosting and clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell arrays are used to increase memory density, then memory capacity is improved, but the area occupied by peripheral circuitry increases
Solution Approach 1:
The capacitor structure transitions from a planar two-dimensional layout to a three-dimensional stacked configuration, where multiple conductive layers are arranged vertically above each other. This dimensional change allows the capacitor to achieve greater capacitance density by utilizing the vertical space, thereby reducing the horizontal area required for the peripheral circuitry while maintaining the necessary electrical storage capacity.
2Ease of manufacture
If conventional planar capacitor structures are used, then manufacturing is simpler, but the area occupied by peripheral circuitry increases
Solution Approach 1:
The capacitor structure transitions from a planar two-dimensional layout to a three-dimensional stacked configuration, where multiple conductive layers are arranged vertically above each other. This dimensional change allows the capacitor to achieve greater capacitance density by utilizing the vertical space, thereby reducing the horizontal area required for the peripheral circuitry while maintaining the necessary electrical storage capacity.
3Area of stationary object
If vertical stacking of conductive layers is implemented, then area occupied by peripheral circuitry is reduced, but device complexity increases
Solution Approach 1:
The capacitor is segmented into multiple discrete conductive layers (first conductive layer, second conductive layer, third conductive layer, etc.) that are stacked vertically and separated by insulating layers. Each layer can be independently formed and controlled, allowing the complex three-dimensional structure to be built up systematically through sequential fabrication steps, thereby managing the overall device complexity.
Solution Approach 2:
The conductive layers in the stacked capacitor structure can serve multiple functions: they form the capacitor electrodes, provide electrical connections to other circuit elements, and can be integrated with the memory cell array structure. This multi-functionality reduces the need for separate dedicated structures, thereby managing complexity while achieving area reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the area occupied by peripheral circuitry, enabling more compact and efficient semiconductor devices while maintaining the necessary voltage and clock signal requirements for memory cell arrays.
Implementation Method 1
The first capacitor is composed of capacities between plural first conductive layers that are arrayed with a set pitch perpendicularly to the substrate
Data Source
AI summary
A semiconductor device comprises a stacked layer memory block and associated peripheral circuits, such as a booster circuit, in stacked layer arrangements. The booster circuit includes plural rectifier cells that are series-connected and plural first capacitors. The plural first capacitors receive a first clock signal on one end, and the other ends thereof are each connected to one end of a different rectifier cell. Each first capacitor is composed of plural first conductive layers that are arrayed with a set pitch perpendicular to the substrate. Either the even numbered or the odd numbered first conductive layers are supplied with the first clock signal. The other of the even numbered or odd numbered first conductive layers are each individually connected to one end of a different rectifier cell.