Nonvolatile Memory Device Row Decoder Segmentation
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Solution Overview
Problem
As the degree of integration of nonvolatile memory devices increases, the load on the high voltage generator also increases, resulting in a larger size for the pumping capacitor, which occupies a significant area in the pump circuit.
Innovation Solution
The nonvolatile memory device is designed with a configuration where multiple row decoders corresponding to memory blocks are divided into upper and lower groups, with local decoder switches controlling the global word lines, reducing the load on the high voltage generator and thus the size of the pumping capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of nonvolatile memory devices is increased, then the memory capacity and functionality are improved, but the load on the high voltage generator increases, requiring a larger pumping capacitor
Solution Approach 1:
The row decoders are divided into upper and lower groups, with each group serving specific memory blocks. This segmentation allows the high voltage generator to supply voltage to only one group at a time, effectively halving the load and enabling the use of a smaller pumping capacitor while maintaining high integration capacity
2Adaptability or versatility
If all row decoders are continuously supplied with high voltage, then all memory blocks can be accessed, but the load on the high voltage generator increases significantly
Solution Approach 1:
The system dynamically switches between upper and lower row decoder groups using local decoder switches. At any given time, only one group is activated and supplied with high voltage, while the other is deactivated. This dynamic switching maintains full memory accessibility while reducing the instantaneous power load on the high voltage generator
Data Source
AI summary
A nonvolatile memory device includes a plurality of memory blocks vertically arranged, first and second row decoder groups configured to couple first and second local global word lines and the word lines of upper memory blocks among the plurality of memory blocks, third and fourth row decoder groups configured to couple third and fourth local global word lines and the word lines of lower memory blocks among the plurality of memory blocks, a first local decoder switch configured to couple a plurality of global lines and the first or second local global word lines, a second local decoder switch configured to couple the plurality of global lines and the third or fourth local global word lines, and a high voltage generator configured to supply operating voltages to the plurality of global word lines.