Self-Calibration Circuit for Nonvolatile Memory Reference Current
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Solution Overview
Problem
Current self-calibration methods for nonvolatile memory reading circuits face challenges in achieving high reliability without increasing circuit area or test cost, particularly in addressing process deviations that can cause current imbalances between '1' and '0' states, leading to potential misreadings across different corners.
Innovation Solution
A self-calibration method and circuit that stores binary trimming data in a bit-pair form, where each digit is represented by 2-digit different binary numbers '0' and '1' in a changed order, using a trimming data storage module, sense amplifier module, logic judgment module, and scanning module to regulate the reference current, ensuring equal quantities of '0' and '1' outputs, thus stabilizing the reference current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polycrystalline fuse is adopted for trimming, then the reference current can be adjusted for different chips, but the number of PAD increases, thus increasing chip area and test cost
Solution Approach 1:
The patent merges the trimming function with existing memory cells by storing trimming data in the same memory array structure. Instead of adding separate fuse components, the solution combines the reference current adjustment capability with the existing memory cell architecture, thereby avoiding additional chip area while maintaining reliability.
Solution Approach 2:
The patent makes the memory cells serve multiple functions: they both store normal data and store trimming data for reference current adjustment. By encoding trimming data in a bit-pair form within the existing memory structure, the same hardware resources are utilized for dual purposes, eliminating the need for dedicated fuse components and reducing chip area.
2Measurement precision
If laser calibration is adopted, then the reference current can be precisely calibrated, but test equipment investment and test cost significantly increase
Solution Approach 1:
The patent performs calibration data preparation in advance by storing the determined trimming data into the memory cells during manufacturing. This preliminary action eliminates the need for expensive real-time laser calibration equipment during testing, as the calibration information is pre-loaded into the memory structure that can then be read and applied without additional precision equipment.
Solution Approach 2:
The patent uses software-based trimming data stored in memory cells to replace the need for physical laser calibration. The trimming data, which represents the calibration information, is copied into the memory array in bit-pair form, allowing the system to achieve precise reference current calibration through data rather than through expensive laser equipment.
3Reliability
If a differential nonvolatile memory is adopted, then each data bit is stored using two physical cells, but the additional storage module increases chip area and requires additional test
Solution Approach 1:
The patent merges the differential storage concept with the existing memory array by using bit-pair encoding within the same memory structure. Instead of adding separate differential memory modules, the solution combines the redundancy and reliability benefits of differential storage with the existing single-module memory architecture, avoiding additional chip area while maintaining data integrity.
Data Source
AI summary
A self-calibration circuit of a nonvolatile memory includes a trimming data storage module, a sense amplifier module, a logic judgment module, and a scanning module. The nonvolatile memory circuit includes a memory cell array and the self-calibration circuit of the reading circuit of the nonvolatile memory. Without requiring an additional fuse or differential unit, the self-calibration circuit of a nonvolatile memory solves a deadlock problem securely and reliably without increasing circuit area and test cost, and be widely applied to OTP, MTP and EEPROM of various processes or various nonvolatile memories such as Flash EEPROM, MRAM, and FeRAM.