Non-Volatile Memory Cell Fuse Antifuse Series Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional non-volatile programmable memory arrays face limitations in density and power consumption due to the need for individual write driver circuits for each memory cell, which also results in state detection margin errors and increased silicon area requirements.
Innovation Solution
A non-volatile programmable memory cell design that combines a two-terminal fuse and a three-terminal antifuse, allowing for shared power rails and a single common write driver circuit, enabling high-density memory arrays with low operational power consumption and improved state detection noise margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If each memory cell has its own write driver circuit, then programming capability is ensured, but silicon area increases and density decreases
Solution Approach 1:
Multiple memory cells share a common write driver circuit through the use of select signals that enable only the intended memory cell to be programmed at any given time. This merging of write driver resources across multiple cells reduces the total silicon area required while maintaining individual programming capability for each cell.
Solution Approach 2:
The write driver circuit operates dynamically by receiving select signals that change over time to activate different memory cells. The circuit transitions between serving different cells based on control signals, allowing one physical write driver to serve multiple logical memory cells through time-multiplexed operation.
2Ease of manufacture
If each memory cell has its own write driver circuit, then programming capability is ensured, but memory density is limited
Solution Approach 1:
The patent merges write driver functionality across multiple memory cells by using a shared write driver circuit controlled by select signals. This allows N memory cells to share 1 write driver circuit, effectively increasing memory density by a factor of N while preserving individual programming capability through selective activation.
Solution Approach 2:
The common write driver circuit is designed to be universal, capable of programming any memory cell in the array when activated by the appropriate select signal. This multi-functional design allows a single write driver to serve multiple memory cells, increasing overall memory density without sacrificing programming capability.
3Measurement precision
If read sensing circuits are provided for each memory cell, then state detection accuracy is improved, but silicon area and power consumption increase
Solution Approach 1:
Multiple memory cells share common read sensing circuits through the use of select signals that enable only the intended memory cell to be read at any given time. This merging of sensing resources reduces the total silicon area required for read circuitry while maintaining accurate state detection capability for each individual cell.
4Quantity of substance
If memory cells draw different current depending on logic state, then storage capability is provided, but power consumption varies undesirably
Solution Approach 1:
The patent employs antifuse structures that, when programmed, change their electrical parameters (resistance, current characteristics) to establish stable logic states. The use of complementary fuse and antifuse elements allows the circuit to maintain consistent power consumption characteristics regardless of the stored logic state, as the complementary nature of the structures balances the current draw.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a high-density non-volatile programmable memory array with reduced power consumption and simplified circuitry, overcoming the limitations of conventional arrays by allowing multiple programming states with minimal power changes.
Implementation Method 1
the alterable element is subjected to specific voltage, current, or voltage-current (power) condition
Implementation Method 2
All integrated circuit non-volatile programmable memory cells include an alterable element that can be altered from a first condition to a second condition, and which retains its second condition even when power is turned off
Data Source
AI summary
A non-volatile one time programmable memory cell couples in series a two terminal fuse and a three terminal antifuse. The non-volatile one time programmable memory cell includes a memory cell write enable node and a memory cell output node. The non-volatile one time programmable memory cell includes fuse having a first node and a second node, and an antifuse having a trigger node, a first node, and a second node. The trigger node is coupled to the memory cell write enable node. The first node of the antifuse and the second node of the fuse are coupled to the memory cell output node. First and second voltages appearing at the memory cell output node are indicative of first and second binary states of the memory cell. A plurality of such memory cells can be included in a non-volatile programmable memory array. A non-volatile programmable memory cell capable of re-programming is also included.