Configurable-Width Memory Channels for Stacked DRAM
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Solution Overview
Problem
Conventional memory systems face inefficiencies due to fixed-width data interfaces, where multiple DRAM devices are accessed in lockstep using a shared bus, leading to inefficient memory accesses, especially when only a portion of the data is requested, as the memory controller reads and writes in blocks regardless of the actual data needed by the processor.
Innovation Solution
A chip package with individually addressable memory chips via separate command and address buses, allowing for a configurable-width memory channel, where only the necessary memory chips are activated for specific data requests, reducing power consumption and improving access granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DRAM devices are accessed in lockstep using a shared bus, then memory bandwidth is improved, but memory access efficiency deteriorates when only a portion of data is requested
Solution Approach 1:
The patent segments the memory access system by providing separate command and address buses for each memory device, allowing individual addressing and control of each DRAM chip. This enables the memory controller to selectively activate only the necessary memory devices for a given access pattern, rather than activating all devices in lockstep, thereby reducing energy consumption while maintaining high bandwidth capability.
Solution Approach 2:
The patent implements dynamic memory access configuration where the memory controller can adaptively configure which memory devices are activated based on the access pattern. The system transitions from a static lockstep access model to a dynamic model where individual memory devices can be independently controlled and activated only when needed, improving energy efficiency without sacrificing bandwidth.
2Device complexity
If a fixed-width data interface is used, then device complexity is reduced, but adaptability to different data-access patterns deteriorates
Solution Approach 1:
The patent segments the data interface into separate command and address buses for each memory device, allowing flexible configuration of the memory access width. This segmentation enables the system to adapt to different data-access patterns (byte, word, half-word, full-word) without changing the fundamental interface structure, thereby improving adaptability while keeping the device complexity manageable.
Solution Approach 2:
The patent enables parameter changes in the memory access configuration, allowing the memory controller to dynamically adjust the effective data width and access granularity based on the specific memory access requirements. This flexibility is achieved through the separate command and address buses that can be selectively activated, providing adaptability to various data-access patterns.
3Productivity
If all memory chips are activated for every access request, then memory bandwidth is maximized, but power consumption increases
Solution Approach 1:
The patent segments the memory chip activation strategy by providing individual control over each memory device through separate command buses. This allows the memory controller to activate only the subset of memory chips that contain the requested data, rather than activating all chips for every access request, thereby reducing power consumption while maintaining the ability to achieve high bandwidth when needed.
Solution Approach 2:
The patent applies partial action by activating only the necessary memory chips for a given access request rather than activating all chips. This partial activation approach reduces power consumption while still providing sufficient bandwidth for the actual data access needs, avoiding the excessive action of activating the entire memory subsystem for every small access request.
Data Source
AI summary
The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips. More specifically, contacts on each individual memory chip are each directly connected to a distinct set of contacts on the semiconductor die such that the semiconductor die has separate, unique command and address buses to individually address and communicate with each individual memory chip. Individually addressable memory chips that are each accessed via separate command and address buses facilitate a configurable-width memory channel that efficiently supports different data-access granularities.