3D NAND Select Transistor Impurity Grading for Leak Current Control
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Solution Overview
Problem
Conventional three-dimensional semiconductor memory devices face challenges in reducing leak current from unselected strings, which affects the correct reading of selected cells, and there is a trade-off between minimizing leak current and generating hole current due to impurity concentration in select transistors.
Innovation Solution
The nonvolatile semiconductor memory device employs a control circuit to manage the conductivity of select transistors connected to memory strings, using a columnar semiconductor layer and conductive layers to control gate voltages, thereby curbing leak current and boosting unselected memory transistors for effective data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the impurity concentration in the body of the select transistor is lowered, then the leak current is reduced, but the hole current generation becomes insufficient
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration zones within the select transistor body. The first region (near the memory string) has a first impurity concentration while the second region (near the source/drain) has a second impurity concentration. This spatial differentiation allows the first region to minimize leak current while the second region ensures sufficient hole current generation during erase operations.
2Quantity of substance
If the number of stacking layers is increased, then the memory density is improved, but the number of lithography processes increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory architecture to three-dimensional stacked architecture. Memory strings are formed vertically by stacking multiple memory cell layers along the stacking direction, enabling increased memory density without proportionally increasing lithography complexity. The selective removal process in the stacking direction allows formation of through-holes connecting multiple layers in a single lithography step.
3Quantity of substance
If the number of strings connected to one bit line is increased, then the memory capacity is improved, but the leak current from unselected strings increases
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration regions within the select transistor body. The first region has a lower impurity concentration to minimize leak current from unselected strings, while the second region has a higher impurity concentration to ensure sufficient hole current generation during erase operations. This spatial differentiation allows the select transistor to effectively control leak current even when many strings are connected to one bit line.
Data Source
AI summary
A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.