Shared Level Shift Circuits in Non-Volatile Memory Row Drivers
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Solution Overview
Problem
The existing non-volatile memory technologies require a large number of transistors in the row driving circuit due to each word line being connected to a separate level shift circuit, leading to an oversized chip.
Innovation Solution
Implementing a row driving circuit with shared level shift circuits, where multiple word line driving circuits share a limited number of level shift up and level shift down circuits, each driving unit comprising an N-type transistor and two P-type transistors, reducing the overall transistor count and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each word line is connected to a separate level shift circuit, then the word line driving function is reliable, but the chip area becomes oversized
Solution Approach 1:
Multiple word line driving circuits share common level shift circuits (first level shift circuit 57a, second level shift circuit 59a) instead of each having dedicated level shift circuits. This merging reduces the total number of level shift circuits from 8 (one per word line driving circuit) to 2 (shared across all word line driving circuits), significantly reducing chip area while maintaining reliable word line driving through the shared architecture
Solution Approach 2:
The first level shift circuit 57a and second level shift circuit 59a serve multiple word line driving circuits simultaneously, making these level shift circuits universal resources. Each level shift circuit can be accessed by multiple word line driving circuits through the row driving circuit 46, allowing one level shift circuit to perform the function of multiple dedicated level shift circuits
2Ease of operation
If a large number of transistors are used in level shift circuits for each word line, then the level shift function is complete, but the transistor count and chip complexity increase
Solution Approach 1:
The patent merges the level shift functionality into shared circuits that serve multiple word line driving circuits. Instead of implementing complete level shift circuits (with 6 transistors each) for every word line, the design combines level shift up and level shift down functions into two shared circuits that can be time-multiplexed across all word lines, reducing total transistor count while maintaining complete level shift functionality
Solution Approach 2:
The row driving circuit 46 dynamically controls access to the shared level shift circuits 57a, 59a based on which word line driving circuit is currently active. This dynamic time-multiplexing allows the same physical level shift circuits to serve multiple logical word lines sequentially, reducing hardware complexity while maintaining full functionality for each word line operation
Data Source
AI summary
Non-volatile memory includes a row driving circuit with shared level shift circuits, so as to minimize the chip area of the non-volatile memory. The row driving circuit includes a plurality of word line driving circuits, a plurality of level shift high circuits, and a plurality of level shift low circuits. The plurality of word line driving circuits share the plurality of level shift high circuits and the plurality of level shift low circuits. Each word line driving circuit includes a plurality of driving units, a level shift high circuit, and a level shift low circuit. The plurality of driving units share the level shift high circuit and the level shift low circuit of the word line driving circuit.