Simultaneous Programming of Both SONOS Transistors in nvSRAM
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Solution Overview
Problem
Current methods cannot simultaneously program both SONOS transistors in a non-volatile Static Random Access Memory (nvSRAM) cell, which limits the efficiency of endurance testing and memory operations.
Innovation Solution
A method for programming both non-volatile memory locations in an nvSRAM cell is provided, involving a tri-gate structure with recall and store transistors, where both SONOS transistors are erased and then programmed using specific voltage and pulse applications to the word line, bit lines, and power nodes, allowing simultaneous programming of both tri-gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional separate programming methods are used for each SONOS transistor, then programming can be completed sequentially, but the time required for endurance testing and memory operations increases significantly
Solution Approach 1:
The patent merges the programming operations of both SONOS transistors into a single unified process. By applying a common programming voltage to both transistors simultaneously through shared word lines and bit lines, the method combines what were previously separate sequential operations into one concurrent operation, thereby doubling the programming throughput and significantly reducing endurance testing time.
Solution Approach 2:
The patent performs preliminary actions by pre-configuring the memory cell state before programming. Specifically, it sets the bit lines to appropriate voltage levels (one high, one low) and ensures the selected memory location is properly addressed before applying the programming voltage. This preliminary setup enables both transistors to be programmed simultaneously without interference, resolving the timing conflict that would otherwise require sequential operation.
2Productivity
If both SONOS transistors are programmed simultaneously, then endurance testing efficiency improves, but the complexity of voltage application and control signals increases
Solution Approach 1:
The patent utilizes the existing multi-functional nature of the memory cell components to achieve simultaneous programming. The word lines and bit lines that normally serve single-purpose functions are made multi-functional, allowing them to participate in programming both SONOS transistors concurrently. This approach leverages the inherent symmetry and shared structure of the memory cell design, avoiding the need for additional dedicated control circuits.
Solution Approach 2:
The patent changes the voltage parameters of existing signals to enable simultaneous programming. By adjusting the voltage levels on bit lines (setting one to high and one to low) and applying a specific programming voltage to the control gate, the system transforms the operational parameters to allow both transistors to be programmed at the same time. This parameter manipulation approach avoids increasing hardware complexity while achieving the desired simultaneous operation.
3Reliability
If the volatile SRAM cell is isolated from the non-volatile portion, then programming can proceed without interference, but the overall memory operation flexibility is reduced
Solution Approach 1:
The patent applies segmentation by logically separating the programming operation from the volatile SRAM cell while maintaining physical connectivity. The method segments the programming process into distinct phases: first isolating the non-volatile portion for programming by controlling the state of coupling transistors, then allowing the volatile cell to remain operational. This segmentation enables independent programming of the non-volatile section without disrupting overall memory flexibility.
Solution Approach 2:
The patent employs periodic action through time-multiplexed operation modes. During programming operations, the coupling between volatile and non-volatile portions is temporarily controlled to prevent interference. During normal read/write operations, full connectivity is restored. This periodic switching between isolated and connected states ensures programming reliability while maintaining operational flexibility, as the system dynamically adapts its connectivity based on the current operation type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the time required for endurance testing by enabling simultaneous programming of both SONOS transistors, enhancing the efficiency of memory operations and reducing the time needed for testing.
Implementation Method 1
A voltage is applied to the word line sufficient to turn the word line to an active state so as to discharge the internal data nodes of the SRAM cell to ground. A voltage is then applied to each store transistor in the first and second tri-gate structures sufficient to turn on each store transistor. Finally, a programming pulse and programming voltage are applied to each SONOS transistor
Data Source
AI summary
A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.