Page Buffer Circuit Shared Sensing Node Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high-capacity downscaled memory devices has led to the development of three-dimensional (3D) memory devices, where the memory cell array and peripheral circuit are arranged vertically. This requires a reduction in the area of the memory cell array and, particularly, the page buffer circuit, which occupies a significant area in the peripheral circuit.
Innovation Solution
The proposed solution involves a memory device with a reduced number of transistors in the page buffer circuit. This is achieved by using a multi-stage structure for the page buffer units and cache latches, where the cache latches include first and second tri-state inverters connected in common to a combined sensing node. During data dumping operations, the tri-state inverters are selectively enabled to transmit and restore data, reducing the number of transistors needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the page buffer circuit uses a conventional structure with separate sensing nodes for each cache latch, then data integrity is maintained, but the area occupied by the page buffer circuit increases significantly
Solution Approach 1:
The patent combines multiple sensing nodes into a single shared sensing node that is commonly connected to multiple cache latches. This merging approach reduces the total number of sensing nodes required, thereby decreasing the area occupied by the page buffer circuit while maintaining data integrity through selective activation of individual cache latches during data dumping operations
Solution Approach 2:
The patent segments the data dumping operation into multiple sections with different activation states for tri-state inverters. During the first section, only specific tri-state inverters are activated while others remain inactive, allowing selective data transmission to individual cache latches. This segmentation enables the shared sensing node to serve multiple cache latches without interference, reducing overall circuit area
2Area of stationary object
If the number of transistors in the page buffer circuit is reduced, then the area of the page buffer circuit decreases, but the capability to maintain data integrity during operations may be compromised
Solution Approach 1:
The patent employs dynamic control of tri-state inverters through selective activation during different sections of data dumping operations. The tri-state inverters can be enabled or disabled based on operational requirements, allowing the circuit to adapt its functionality to maintain data integrity while using fewer transistors. This dynamic approach ensures that only necessary data paths are active at any given time, preserving reliability with reduced hardware
Solution Approach 2:
The shared sensing node acts as an intermediary between multiple cache latches and the memory cell array. It mediates data transmission by selectively connecting to different cache latches through controlled tri-state inverters, ensuring that data integrity is maintained during dumping operations while reducing the total number of direct connections required
3Area of stationary object
If multiple cache latches share a common sensing node, then the area of the page buffer circuit is reduced, but the control complexity of data dumping operations increases
Solution Approach 1:
The patent implements periodic action by dividing the data dumping operation into distinct sections with specific activation patterns for tri-state inverters. During the first section, certain inverters are activated while others are inactive, and during the second section, the activation pattern changes. This periodic control structure manages the complexity of controlling multiple shared cache latches through a systematic, time-based approach
Data Source
AI summary
A memory device includes a memory cell array, a plurality of page buffer units connected to the memory cell array and connected in common to a combined sensing node, and a plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches including a first cache latch and a second cache latch connected in common to the combined sensing node. In a first section of a data dumping operation on the first cache latch, first and second tri-state inverters included in the first cache latch are enabled to transmit data to the first cache latch, and third and fourth tri-state inverters included in the second cache latch are disabled. In a second section of the data dumping operation on the first cache latch, the third and fourth tri-state inverters are sequentially enabled to restore data previously stored in the second cache latch.