Variable-Size Pass Transistors in 3D NAND Row Decoders
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Solution Overview
Problem
The increasing degree of integration in semiconductor memory devices, particularly in 3D NAND flash memory, leads to a larger area for the pass transistor unit (TR) within the row decoder, which acts as a bottleneck limiting chip size reduction while maintaining operating characteristics.
Innovation Solution
The semiconductor memory device incorporates a pass transistor unit with multiple pass transistors having different channel areas based on voltage levels of driving signals, allowing for a reduced area and layout length, and utilizing a specific fabrication method involving isolation films, channel trenches, and field stop regions to enhance current driving power and prevent characteristic deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased in 3D NAND flash memory, then memory capacity is improved, but the area of the pass transistor unit increases causing chip size expansion
Solution Approach 1:
The patent transitions from planar 2D transistor layout to vertical 3D transistor stacking, where multiple transistor channels are stacked in the vertical dimension above the same footprint area. This allows the pass transistor unit to drive higher capacity memory cells without proportionally increasing the horizontal chip area, as the additional transistor channels utilize the vertical space above the substrate.
Solution Approach 2:
The patent changes the channel area parameter of pass transistors based on their position and function within the stacked structure. Different pass transistors in the vertical stack have different channel areas optimized for their specific driving requirements, allowing efficient area utilization while maintaining the ability to drive high-capacity memory cells connected in series.
2Ease of manufacture
If uniform channel area is used for all pass transistors, then manufacturing is simplified, but operating characteristics deteriorate due to insufficient current driving power for high voltage signals
Solution Approach 1:
The patent applies different channel area dimensions to different pass transistors based on their local functional requirements. Pass transistors that need to drive higher voltage signals have larger channel areas, while those driving lower voltage signals have smaller channel areas. This localized optimization ensures each transistor has sufficient current driving power for its specific role without requiring all transistors to be uniformly large, thus maintaining manufacturing feasibility while improving operating characteristics.
Data Source
AI summary
A semiconductor memory device includes a memory cell array (MCA) and a pass transistor unit (PTU). The MCA includes memory block(s) that has source selection line(s) (SSL), word lines (WLs), drain selection line(s) (DSL), and dummy WL(s) (DWL). The PTU includes source pass transistor(s) to selectively transmit a source driving signal (source DS) to the SSL, memory pass transistors (MPTs) to selectively transmit a WL DS to the WLs, respectively, drain pass transistor(s) (PT) to selectively transmit a drain DS to the DSL, and dummy PT(s) to selectively transmit a DWL DS to the DWL. The source DS, the WL DS, the drain DS, and the DWL DS may each be associated with a respective voltage range. Sizes of the source PT, the MPTs, the drain PT, and the dummy PTs are set based on the respective voltage ranges.