Flash Memory Reference Current Circuit with Temperature Compensation
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Solution Overview
Problem
Conventional flash memory devices face issues with cell disturb and temperature-dependent reference current variations, leading to degraded read access times due to the use of reference flash memory cells for generating reference currents.
Innovation Solution
A pair of parallely connected NMOS transistors with different voltage ratings is used to generate a temperature-compensated reference current for the sense amplifier, eliminating the need for a reference flash memory cell and reducing temperature coefficient variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference flash memory cell is used to generate reference current, then the read operation can be performed, but the reference current drifts over time due to cell disturb issues
Solution Approach 1:
The patent extracts the reference current generation function from the flash memory cell and implements it using a separate circuit consisting of a bandgap voltage reference and a current mirror circuit. This separation allows the reference current to be generated without subjecting reference storage cells to read disturbances, thereby eliminating the drift issue while maintaining read functionality.
Solution Approach 2:
The patent uses a current mirror circuit to copy the reference current from a stable bandgap voltage reference to the sense amplifier. This copying mechanism provides a stable reference current that does not suffer from cell disturb issues, as the reference is generated electrically rather than stored in vulnerable memory cells.
2Device complexity
If an NMOS transistor is used to generate reference current, then the circuit is simple, but the reference current has large temperature variation
Solution Approach 1:
The patent changes the operating parameters of the NMOS transistor by biasing it with a bandgap voltage reference that has been specifically designed to compensate for temperature effects. The bandgap circuit adjusts the voltage parameters to maintain a stable reference current across temperature variations, reducing the temperature coefficient from large variations to near-zero.
Solution Approach 2:
The patent combines multiple circuit elements (bandgap voltage reference, current mirror, and NMOS transistor) into a composite reference current generation system. This composite structure leverages the temperature-stabilizing properties of the bandgap circuit to compensate for the inherent temperature sensitivity of the NMOS transistor, achieving overall temperature insensitivity.
3Reliability
If a reference flash memory cell is used, then reference current can be generated, but large silicon area is consumed
Solution Approach 1:
The patent extracts the reference current generation function from the flash memory cell array and implements it using a compact electrical circuit. This extraction eliminates the need for dedicated reference storage cells, thereby freeing up significant silicon area while maintaining reliable reference current generation through the bandgap and current mirror circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution prevents cell disturb issues and achieves a reference current with zero or near-zero temperature coefficient, enhancing the reliability and accuracy of read operations in flash memory devices.
Implementation Method 1
the resulting reference current has a resulting temperature coefficient that is less than one tenth the temperature coefficient of the current generated by the NMOS transistor alone
Data Source
AI summary
A flash memory device uses a pair of parallely connected NMOS transistors with different voltage ratings to generate the reference current for the sense amplifier used in the read out operations. The reference current thus generated is temperature compensated with zero or near-zero temperature coefficient. In some embodiments, the pair of parallely connected NMOS transistors includes a high voltage NMOS transistor and a low voltage NMOS transistor or NMOS transistors with different gate oxide thicknesses.