Split Read and Write Bitlines for NVM Performance
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Solution Overview
Problem
Conventional non-volatile memory (NVM) bitcells face design conflicts due to shared bitlines for read and write operations, leading to low read speeds, high read currents, and increased complexity in peripheral circuitry, as they struggle to accommodate both high and low voltage operations effectively.
Innovation Solution
Separate physical bitlines for read and write operations are introduced, with low capacitance bitlines for reading and low resistance bitlines for writing, allowing for improved performance and reduced die area usage by optimizing bitline design and geometry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bitline is shared for both read and write operations, then device complexity is reduced, but read speed decreases and read current increases due to the need to accommodate both high voltage write operations and low voltage read operations
Solution Approach 1:
The patent divides the single shared bitline into two separate physical bitlines: a first bitline optimized for write operations and a second bitline optimized for read operations. This segmentation allows each bitline to be independently designed with appropriate electrical characteristics, resolving the conflict between write current requirements and read speed requirements.
Solution Approach 2:
The patent applies different design optimizations to different bitlines based on their specific functional requirements. The write bitline is designed with characteristics suitable for high voltage and large current operations, while the read bitline is designed with characteristics optimized for low voltage and high speed operations. This local quality approach allows each bitline to perform its specific function efficiently.
2Ease of manufacture
If a single bitline is used for both read and write operations, then manufacturing is simplified, but read operation power consumption increases due to high capacitance
Solution Approach 1:
By segmenting the bitline function into separate write and read bitlines, the patent enables the read bitline to be specifically optimized for low capacitance and low power operation, independent of the write bitline's high current requirements.
Solution Approach 2:
The read bitline is specifically designed with local quality optimizations for low power consumption, including minimized capacitance and optimized geometry for low voltage operation, while the write bitline handles high voltage and current requirements separately.
3Adaptability or versatility
If a single bitline accommodates both high voltage write operations and low voltage read operations, then device versatility is maintained, but peripheral circuitry complexity increases
Solution Approach 1:
The patent segments the voltage domains by providing separate bitlines for high voltage write operations and low voltage read operations. This allows peripheral circuitry to be optimized for each voltage domain independently, reducing the complexity of voltage switching and protection circuitry that would be required for a shared bitline.
Solution Approach 2:
Each bitline is designed with local quality characteristics matched to its voltage domain: the write bitline is optimized for high voltage tolerance and current handling, while the read bitline is optimized for low voltage operation. This eliminates the need for complex peripheral circuitry to protect or adapt a single bitline for both voltage levels.
4Power
If low resistance bitlines are used for write operations, then write performance is improved, but read speed decreases due to large bitline capacitance
Solution Approach 1:
The patent segments the bitline function to allow the write bitline to be optimized for low resistance and high current capability, while the read bitline is separately optimized for low capacitance and high speed operation. This eliminates the direct trade-off between write current capability and read speed that exists in shared bitline designs.
Solution Approach 2:
The write bitline is designed with local quality characteristics for low resistance and high power handling, while the read bitline is designed with local quality characteristics for low capacitance and high speed response. Each bitline's electrical characteristics are locally optimized for its specific function without compromise.
Data Source
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AI summary
Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations.