DDR Nonvolatile Memory Architecture with Direct Register Access
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Solution Overview
Problem
Current storage devices, such as Double Data Rate (DDR) SDRAM, do not provide permanent storage and are insufficient for handling the increased demand for faster data transfer and storage due to advancements in digital technologies, particularly in wireless communications and computing systems.
Innovation Solution
The implementation of a Double Data Rate (DDR) nonvolatile memory architecture that supports data transfers on both rising and falling edges of a clock cycle, accommodating legacy flash functions while performing foreground reads and background write operations, and directly accessing registers to manage data coherence and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DDR SDRAM is used for fast data transfer, then data transfer speed is improved, but permanent storage capability is lost
Solution Approach 1:
The patent combines DDR SDRAM and legacy flash memory into a single integrated device. The DDR interface controller manages both the volatile memory array for high-speed operations and the non-volatile flash memory for permanent storage, allowing the device to function as both fast temporary storage and reliable permanent storage within one component.
Solution Approach 2:
The integrated device performs multiple functions: it operates as high-speed DDR memory for active data processing, as non-volatile flash storage for permanent data retention, and provides seamless data transfer between the two memory types. This multi-functionality resolves the contradiction by making a single device capable of both fast transfer and permanent storage.
2Ease of operation
If legacy flash functions are maintained for compatibility, then ease of operation is improved, but data transfer bandwidth is limited
Solution Approach 1:
The DDR interface controller acts as an intermediary layer that translates between legacy flash command protocols and high-speed DDR memory operations. This allows legacy applications to continue using familiar flash interfaces while the controller internally manages data transfers through the high-bandwidth DDR interface, maintaining compatibility without sacrificing performance.
Solution Approach 2:
The device dynamically switches between legacy flash access modes and high-speed DDR modes based on the type of operation required. For compatibility-critical operations, it uses legacy protocols; for performance-critical data transfers, it utilizes the high-bandwidth DDR interface, optimizing both ease of operation and productivity.
3Productivity
If foreground reads and background writes are implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The memory device is segmented into distinct functional areas: a volatile DDR SDRAM array for foreground operations, a non-volatile flash memory array for background operations, and a control unit that manages the separation and coordination between them. This segmentation allows independent optimization of each section while maintaining overall system productivity.
Solution Approach 2:
The integrated controller automatically manages the complex coordination between foreground reads and background writes without requiring external intervention. It autonomously handles data buffering, transfer timing, and memory coherence, reducing the perceived complexity for users while maintaining high productivity through parallel operations.
Data Source
AI summary
A Double Data Rate (DDR) nonvolatile memory for use with a wireless device. A host processor transfers commands and data through a DDR interface of the nonvolatile memory. The DDR nonvolatile memory implements legacy flash functions while maintaining DDR behavior.