Row Decoder Transistor Stacking for High Voltage Reliability
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Solution Overview
Problem
As memory device storage capacity increases, reducing the pitch between adjacent wordlines leads to transistor deterioration in wordline driving circuits when high voltage is applied, affecting performance and reliability.
Innovation Solution
The implementation of a row decoder with multiple main wordline driving circuits, where transistors functionally corresponding to each other are disposed in different rows or locations, increasing gate width and gap between the gate and contact, to prevent deterioration and enhance reliability without significant size sacrifice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor sizes are reduced to accommodate smaller cell pitch, then storage capacity increases, but transistor performance deteriorates when high voltage is applied
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar transistor arrangement to a three-dimensional stacked configuration. Transistors are arranged in multiple vertical stacks (first stack, second stack, third stack) with different gate lengths (L1, L2, L3) and overlapping active regions. This vertical stacking allows the circuit to accommodate smaller cell pitch while maintaining transistor performance through the extended vertical dimension, thereby resolving the contradiction between increased storage capacity and maintained transistor reliability under high voltage.
2Reliability
If transistors are placed in different rows to prevent deterioration, then reliability improves, but device complexity increases
Solution Approach 1:
The patent merges multiple transistor stacks into a unified three-dimensional structure where the first, second, and third transistor stacks share common active regions and are integrated within a single circuit block. This merging approach distributes transistors across different vertical levels (rows) to prevent deterioration through varied gate lengths and overlapping regions, while the overall integration minimizes the increase in device complexity by utilizing shared structural elements.
Data Source
AI summary
A row decoder includes first and second main wordline driving circuits, which are configured to generate respective first and second driving signals onto corresponding first and second main wordlines extending adjacent to each other. In addition, a first transistor within the first main wordline driving circuit and a second transistor within the second main wordline driving circuit have the same function, but extend in different rows when viewed in a direction perpendicular to a substrate on which the first and second main wordlines are formed.