Memory Block Testing via Page-Level Programming Time Compensation

The patent segments the block evaluation into individual page performance assessments. Instead of treating the block as a single unit where one slow page fails the entire block, the method evaluates each page's programming time independently and allows the block to pass if the majority of pages meet the speed requirement, with slower pages compensated by faster ones.

The patent changes the evaluation parameter from binary (pass/fail based on any single page) to a distributed assessment where programming times of multiple pages are compared and averaged. This parameter transformation allows compensation between fast and slow pages, reducing unnecessary block failures while maintaining programming speed guarantees.

The patent segments the block into individual pages for independent timing evaluation. By assessing each page's programming time separately and allowing compensation between pages, the method avoids time-consuming repairs of entire blocks that would otherwise be failed due to single slow pages.

The patent transforms the evaluation from a strict per-page threshold check to a comparative assessment where pages are evaluated relative to each other. This parameter change enables blocks with some slow pages to pass if compensated by faster pages, eliminating unnecessary repair cycles and reducing manufacturing time.

The patent changes the quality control parameter from individual page threshold enforcement to a block-level statistical assessment. By evaluating whether the majority of pages meet timing requirements and allowing compensation, the method maintains quality control while reducing the complexity associated with frequent block repairs.

The patent merges individual page performance evaluations into a unified block assessment. Instead of treating each page independently with strict pass/fail criteria, the method combines page timings into an overall block evaluation, reducing repair frequency and associated complexity.