Flash Memory Page Buffer Circuit with Shared Register

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Solution Overview

Problem

The conventional page buffer circuit in flash memory devices is inefficient due to its complex structure, which increases circuit area and reduces operational performance, particularly when handling multi-level cells that require separate registers for higher and lower data bits during reading and programming operations.

Innovation Solution

A simplified page buffer circuit design that alternates the use of higher-bit and lower-bit registers for reading data bits, utilizing a shared sensing node and switching circuits to reduce circuit complexity and area, and includes a precharge circuit, bitline selection, and output drive circuit to manage voltage levels and data transfer efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If separate higher-bit and lower-bit registers are used for multi-level cell operations, then data storage capability is improved, but circuit area and device complexity increase

Engineering Contradiction:

Improvedata storage capabilityVSAvoidcircuit structure complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges the higher-bit register and lower-bit register into a single unified register structure. The same register is used to store both higher data bits and lower data bits by dynamically configuring its storage nodes, eliminating the need for physically separate register circuits and reducing overall circuit complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The unified register is designed to serve multiple functions: it can store higher data bits during programming operations, store lower data bits during read operations, and transfer data between different voltage levels. This multi-functional design replaces the need for dedicated separate registers for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Quantity of substance

If separate higher-bit and lower-bit registers are used for multi-level cell operations, then data storage capability is improved, but circuit area increases

Engineering Contradiction:

Improvedata storage capabilityVSAvoidcircuit area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Difficulty of detecting and measuring

If the higher-bit register is configured to detect only voltage levels, then sensing simplicity is improved, but the ability to store inverse data values is lost

Engineering Contradiction:

Improvesensing simplicityVSAvoiddata storage flexibility

Core Design Contradiction:

Difficulty of detecting and measuringVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic configuration capability to the register, allowing it to switch between different operational modes. The register can be configured to detect voltage levels during sensing operations and switch to storing inverse data values during programming operations, achieving both sensing simplicity and data storage flexibility through time-multiplexed functionality.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the register based on the required function. By adjusting control signals and voltage levels, the register transitions between detection mode and storage mode, enabling it to perform both voltage level detection and inverse value storage without requiring separate dedicated circuits.

Inventive Principle:

Principle #35Parameter changes

4Productivity

If NMOS transistors are used in data output circuits for both higher and lower data bits, then data output capability is improved, but circuit area and complexity increase

Engineering Contradiction:

Improvedata output capabilityVSAvoidcircuit structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the data output circuits for higher and lower data bits into a single shared output circuit. The same NMOS transistor-based output circuit is used to drive both higher data bits and lower data bits by selectively connecting it to the appropriate register outputs, eliminating redundant transistors and simplifying the overall circuit structure.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The unified data output circuit is designed to handle multiple data types. It can output higher data bits during programming operations and lower data bits during read operations, achieving multi-functionality with a single circuit implementation rather than requiring separate dedicated output circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7508709B2Page buffer circuit with reduced size and methods for reading and programming data with the same

Publication Date: 2009.03.24 SK HYNIX INC

AI summary

A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation.