Flash Memory Source Discharge Transistor Boost Voltage Control
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Solution Overview
Problem
In conventional flash memory arrays, the limited discharge current from source discharge transistors can lead to incorrect data interpretation and reduced reading speed due to excessive current from memory cells in a page group being '1', causing the source discharge transistor to exceed its maximum capacity.
Innovation Solution
A flash memory apparatus and method that includes a source discharge transistor, a pre-charge unit, a boost unit, and a control unit, where a boost voltage greater than the pre-charge voltage is applied to the source discharge transistor during data reading, enhancing its discharge capability by using a capacitor unit and switching unit to provide a higher voltage level, thereby improving data reading accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the source discharge transistor uses a fixed pre-charge voltage, then the device complexity is low, but the discharge current is insufficient when most memory cells in a page group are '1', leading to incorrect data interpretation and reduced reading speed
Solution Approach 1:
The patent applies dynamics by making the gate voltage of the source discharge transistor variable rather than fixed. The voltage dynamically switches between pre-charge voltage (when fewer cells are '1') and boost voltage (when most cells are '1'), allowing the transistor to adapt its discharge capability to the actual current demand of the memory cell array.
Solution Approach 2:
The patent changes the voltage parameter of the source discharge transistor's gate based on the reading conditions. By detecting whether most memory cells in a page group are '1' and accordingly adjusting the gate voltage from pre-charge level to boost level (higher than pre-charge), the system optimizes the discharge current to match the actual reading requirements.
2Reliability
If the source discharge transistor operates with limited discharge current, then the device complexity remains low, but the correctness of data reading deteriorates when most memory cells are '1'
Solution Approach 1:
The system dynamically adjusts the discharge current capability of the source discharge transistor based on the actual reading conditions. When most memory cells in a page group are '1', the gate voltage is boosted to provide higher discharge current, ensuring accurate data reading without compromising speed.
Solution Approach 2:
The patent changes the operating parameters of the source discharge transistor by applying a boost voltage (higher than pre-charge voltage) to the gate when most memory cells are in the '1' state. This parameter change enables the transistor to deliver sufficient discharge current to maintain both reading correctness and speed.
Data Source
AI summary
A flash memory apparatus and a data reading method thereof are provided. A boost voltage greater than a pre-charge voltage is provided to a gate of a source discharge transistor when a data reading operation is performed on a memory unit, so as to enhance discharge capability of the source discharge transistor.