Dynamic Latch for Multiple Bias Voltages in Memory Page Buffers
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Solution Overview
Problem
Existing memory devices face inefficiencies due to the need for multiple static primary data caches (PDC) to store bias voltages for selective slow program convergence (SSPC) programming, leading to increased size and cost, as well as slower performance.
Innovation Solution
The implementation of an additional dynamic latch in a page buffer to provide two bias voltages associated with both slow and fast SSPC voltages, allowing for the elimination of static PDC latches and enhancing programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple static primary data caches (PDC) are used to store bias voltages for SSPC programming, then the memory device can provide multiple bias voltages, but the page buffer size increases and cost increases
Solution Approach 1:
The dynamic latch is designed to perform multiple functions: it can store different bias voltages (first bias voltage for slow SSPC, second bias voltage for fast SSPC) by selectively coupling different capacitors to the sense node. This single structure replaces what would traditionally require multiple separate PDC latches, achieving multi-functionality without proportionally increasing area.
Solution Approach 2:
The invention uses a dynamic latch with capacitors that can be selectively coupled to the sense node through control logic. This dynamic reconfiguration allows the same hardware structure to provide different bias voltages at different times, replacing static multiple PDC structures with a dynamic single structure that achieves the same functionality with reduced area.
2Adaptability or versatility
If multiple static primary data caches (PDC) are used to store bias voltages, then the memory device can perform SSPC programming, but the programming speed decreases
Solution Approach 1:
The dynamic latch enables fast switching between different bias voltages through controlled capacitor coupling. The control logic can rapidly select which capacitor to couple to the sense node, allowing the system to switch between slow SSPC and fast SSPC modes quickly, thereby improving programming speed compared to static multiple PDC approaches.
Solution Approach 2:
The invention extracts the essential function of storing bias voltages from the traditional static PDC structure and implements it in a dynamic latch with selective capacitor coupling. This extraction allows the system to maintain SSPC programming capability while achieving faster operation through the dynamic nature of the latch.
3Adaptability or versatility
If external PDC latches are used to store bias voltages, then the memory device can provide bias voltages for programming, but the overall device complexity increases
Solution Approach 1:
The invention merges the bias voltage storage function with the existing dynamic latch structure in the page buffer. By integrating the capacitor-based bias storage directly into the page buffer's dynamic latch, the design eliminates the need for separate external PDC latches, thereby reducing device complexity while maintaining the capability to provide multiple bias voltages.
Solution Approach 2:
The dynamic latch in the page buffer is designed to serve multiple purposes: it functions as both the operational latch for data storage and as the bias voltage storage mechanism for SSPC programming. This multi-functionality eliminates the need for separate external PDC latches, reducing overall device complexity.
Data Source
AI summary
A memory device includes a sense amplifier (SA) latch coupled to a sense node. A dynamic latch (DL) is coupled to the SA latch and coupled to sense node. Control logic is coupled to the SA latch and the DL. The control logic causes a pre-program verify voltage to boost the sense node. In response to detecting a high bit value stored in SA latch, the control logic causes a voltage to turn on set transistor(s) of the DL so that a first bias voltage or a second bias voltage is stored at a latch transistor.