Charge Trap Flash Memory Erase Control for Temperature Stability

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Solution Overview

Problem

Charge trap flash memory devices experience increased error frequency and reduced reliability when operating at temperatures outside their verified range due to transient characteristics being affected by temperature, humidity, and electromagnetic forces, leading to malfunctions and shortened lifespan.

Innovation Solution

A method for a charge trap flash memory device that adjusts erase operation conditions based on temperature detection results, including modifying delay time and word line voltage levels, to ensure stable performance and accuracy even at cold temperatures, thereby reducing high voltage stress and extending the device's lifespan.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If erase operation is performed at cold temperature below verified operating range, then erase operation can be executed, but error occurrence frequency increases and reliability deteriorates

Engineering Contradiction:

Improveoperating temperature rangeVSAvoiderase operation reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies dynamics by making the delay time between erase execution and verify operation variable based on temperature conditions. At cold temperatures, the delay time is extended to allow sufficient time for electron/hole stabilization in the charge storage layer, while at normal temperatures the delay time is reduced. This dynamic adjustment of timing parameters enables reliable erase operations across a wide temperature range without compromising erase accuracy.

Inventive Principle:

Principle #15Dynamics

2Speed

If erase verify operation is performed before electron/hole stabilization is secured, then operation speed is maintained, but erase accuracy decreases and errors increase

Engineering Contradiction:

Improveerase operation speedVSAvoiderase verify accuracy

Core Design Contradiction:

SpeedVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by introducing a delay time period between the erase execution interval and the erase verify operation. During this delay time, electrons and holes are allowed to stabilize in the charge storage layer before verification begins. This preliminary stabilization period ensures that the verify operation measures the true erase state without interference from transient charge effects, thereby improving erase accuracy while maintaining acceptable operation speed through optimized delay duration.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If high voltage stress is increased to ensure erase accuracy at cold temperature, then erase reliability improves, but device lifespan shortens

Engineering Contradiction:

Improveerase operation reliabilityVSAvoiddevice lifespan

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent applies parameter changes by adjusting the timing parameters (delay time, erase execution duration) rather than increasing voltage stress to improve erase reliability at cold temperatures. By extending the delay time to allow proper charge stabilization, the patent achieves reliable erase verification without subjecting the device to excessive voltage stress that would accelerate degradation. This parameter optimization maintains device lifespan while ensuring accurate erase operations across temperature ranges.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances erase accuracy and stability, reduces error occurrence, and prolongs the life of the charge trap flash memory device by optimizing erase operations based on temperature, ensuring reliable performance across varying temperatures.

Implementation Method 1

electrons/holes in a charge storage layer become stabilized in terms of energy such that the injection/emission of the electrons/holes to/from the charge storage layer does not occur

Methodology Applied

Scientific EffectEnergy level stabilization:

Implementation Method 2

receiving a temperature detection result; and performing an erase operation based on the temperature detection result

Methodology Applied

Scientific EffectTemperature detection:

Implementation Method 3

the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution interval and the erase verify interval, wherein the erase execution interval changes a level of a word line voltage applied to word lines during the erase execution interval

Methodology Applied

Scientific EffectVoltage level modification:

Data Source

PatentUS8599622B2Charge trap flash memory device and an erasing method thereof

Publication Date: 2013.12.03 SAMSUNG ELECTRONICS CO LTD

AI summary

An erase method of a charge trap flash memory device, the method including receiving a temperature detection result, and performing an erase operation based on the temperature detection result, wherein the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution interval and the erase verify interval, wherein the erase operation changes a level of a word line voltage applied to word lines during the erase execution interval, a length of the delay time, or a level of the word line voltage applied to the word lines during the delay time.