Sense Amplifier Offset Compensation via Trimmable Clamping Circuits

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Solution Overview

Problem

Sense amplifiers in non-volatile memory systems face challenges in accurately reading data due to mismatches in threshold voltages of transistors within clamping circuits, leading to offset issues that cannot be fully compensated by existing offset-compensation methods, especially in semiconductor manufacturing processes where physical characteristics of transistors vary.

Innovation Solution

The implementation of trimmable clamping circuits with a voltage comparator and a controller that adjusts the threshold voltages of the clamping circuits to match those of reference cells, using a combination of main and trimming branch circuits to ensure accurate voltage matching and reduce offset, thereby enhancing the sense amplifier's ability to determine voltage differences between bit lines and reference bit lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If offset sampling or cancelling stage is implemented before actual read operation, then mismatch of sense amplifier circuit is cancelled, but variations of reference cells cannot be cancelled and additional circuit complexity is introduced

Engineering Contradiction:
Improvesense amplifier mismatch cancellationVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines the offset sampling function with the reference cell into a single integrated structure. The reference cell itself performs the offset sampling during normal operation, eliminating the need for separate offset sampling circuits. This merging approach cancels sense amplifier mismatch while avoiding additional circuit complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The reference cell is designed to serve multiple functions: it acts as both the reference for data cell comparison and simultaneously performs offset sampling of the sense amplifier. This multi-functionality eliminates the need for dedicated offset sampling circuits while maintaining mismatch cancellation capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If trimming range is increased to compensate for transistor mismatches, then offset compensation accuracy is improved, but area overhead increases

Engineering Contradiction:
Improveoffset compensation accuracyVSAvoidarea overhead
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent implements dynamic threshold voltage adjustment through controllable switches that connect different trimming branches to the reference cell. This dynamic configuration allows the trimming range to be expanded only when needed, rather than providing maximum trimming capability in all cases, thus reducing average area overhead while maintaining compensation accuracy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The trimming circuit is divided into multiple segments or branches, each providing a portion of the total trimming range. This segmentation allows the circuit to achieve large overall trimming capability while using compact individual segments, reducing the area overhead compared to a single large trimming circuit.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11688436B2Sense amplifier and operating method for non-volatile memory with reduced need on adjusting offset to compensate the mismatch
Publication Date: 2023.06.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11688436B2 patent drawing
  • US11688436B2 patent drawing
  • US11688436B2 patent drawing

AI summary

A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.