3D Memory Device Defect Detection During Erase
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Solution Overview
Problem
Three-dimensional nonvolatile memory devices face reliability issues due to narrow intervals between elements, making defect detection challenging after the product has been shipped.
Innovation Solution
A memory device with stacked memory cells and peripheral circuits that perform erase and defect detection operations, processing memory blocks as bad blocks when defects are detected, and selectively verifying pages with potential defects to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional nonvolatile memory devices are implemented with vertically stacked memory cells to achieve high integration, then storage capacity is improved, but the interval between elements becomes narrow and reliability deteriorates
Solution Approach 1:
The patent performs defect detection operations during the erase operation phase, before the memory device is shipped and before normal operation begins. By detecting defects early in the manufacturing/testing phase rather than during field operation, the system can identify and manage problematic memory blocks proactively, preventing reliability issues from manifesting during actual use.
Solution Approach 2:
The memory device performs self-diagnosis by incorporating defect detection capabilities within the memory device itself. The peripheral circuits include defect detection circuits that can autonomously test memory cells during erase operations, allowing the device to self-identify defects without requiring external testing equipment or intervention.
2Reliability
If defect detection operations are performed on all memory cells, then reliability is improved, but operation time and complexity increase
Solution Approach 1:
The patent performs defect detection operations selectively on certain memory blocks rather than exhaustively testing every single memory cell in the entire memory device. The defect detection is performed on memory blocks that are being erased anyway, and only during time periods when the memory device is not being used for normal operations. This partial testing approach provides sufficient defect detection capability without requiring complete testing of all cells.
Solution Approach 2:
The defect detection operations are performed periodically during erase operations rather than continuously or before every read operation. By utilizing the periodic erase cycles that naturally occur in memory device operation, the system can perform defect checks at appropriate intervals without adding continuous overhead to normal read/write operations.
3Quantity of substance
If narrow intervals between elements are used in 3D structure, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces physical/mechanical defect detection methods with electrical measurement methods. Instead of physically measuring or inspecting the narrow intervals between stacked memory cells, the system uses electrical signals to detect defects by measuring current flow, threshold voltages, or other electrical characteristics during erase and verify operations. This electrical approach is more suitable for detecting defects in tightly packed 3D structures where physical measurement would be extremely difficult.
Data Source
AI summary
A memory device, and a method of operating the memory device, includes a memory block configured to include a plurality of memory cells that are stacked to be spaced apart from each other on a substrate and to include word lines coupled to the plurality of memory cells, and bit lines and a source line coupled to both ends of strings including the plurality of memory cells, and peripheral circuits configured to perform an erase operation on the memory block, wherein the peripheral circuits are configured to perform the erase operation on the plurality of memory cells included in the memory block, and thereafter perform a defect detection operation on memory cells selected from among the plurality of memory cells depending on sizes of the plurality of memory cells.