Read-Only Memories TRIZ Cases

Dual voltage regulators boost well and word line voltages during pull-up intervals to maintain required potential relationships.

A P+/N well junction diode controls programming current through voltage pulses, resolving fabrication defects and ensuring reliable resistance changes.

Peripheral circuitry determines verification start loops based on sensing results, reducing programming time across word lines with varying speeds.

A non-volatile memory controller adjusts programming voltages based on read-back data to configure multi-level cells.

Configurable page size in NAND flash memory banks enables selective plane access, reducing unnecessary erase cycles and improving endurance.

Classifying memory blocks by read time and error occurrence allows setting unique durability parameters, resolving instability from uniform management.

Adaptive select gate scan operations prioritize memory dice based on quality characteristics, reducing latency and improving quality of service.

A memory sub-system controller adapts error-handling sequences based on voltage offset bins to optimize data recovery.

Atomic layer deposited hafnium tantalum oxynitride reduces leakage current while enabling equivalent oxide thickness scaling.

Multi-cell per bit storage compensates for defective anti-fuse cells, ensuring data accuracy despite unpredictable programming conditions.

Sharing even and odd power transistors in a common active region reduces vertical layout length, addressing integration limits from double patterning.

An erasion circuit alters intrinsic characteristics of memory bits to generate a new PUF signature upon power-on.

A CMOS non-volatile memory cell injects hot carriers onto a floating gate to program data with minimal channel current.

Partitioning NAND flash memory into distinct error zones enables adaptive error correction, reducing ECC complexity while maintaining data integrity.

Constant substrate voltages in word line drivers and bit line switches remove parasitic capacitance charging time, accelerating soft program verify cycles.

A shared address counting circuit generates column addresses by latching shared signals across multiple memory banks.

Dynamic bit state assignment minimizes floating gate-to-floating gate coupling in flash memory rows.

Signal processing circuits perform addition and multiplication on RRAM cell pair currents to resolve high temperature data retention issues.

A sense amplifier uses two pre-charged capacitors to compare voltage levels for faster data state determination.

An eFuse one-time programmable memory integrates an I2C slave interface to resolve manufacturing defects from insufficient write-read function review.

Horizontally-elongated lines in insulative tiers block etching action, reducing short risks between conductor tiers.

Programming edge word lines to uniform states suppresses read disturbance and maintains threshold voltage stability across the array.

A current sensing methodology replaces voltage measurement to enable accurate detection of negative threshold states across all bit lines.

Negative voltage pre-biasing on unselected word lines prevents accidental programming of adjacent cells while maintaining high speed for selected strings.

A memory controller schedules reliability countermeasures for nonvolatile semiconductor memory by tracking access processes and skipping redundant operations.

Two-phase programming with a shared buffer reduces device complexity while maintaining uniform programming rates across non-volatile memory cells.

A memory system adjusts programming order based on measured page speeds to optimize threshold voltage distribution.

A nonvolatile memory device applies a stepwise increasing gate voltage to selection cells for parallel data writing.

A charge pump circuit generates voltages using phase signals and enabling signals.

An anti-fuse cell uses an irreversible snapback transistor to create a low resistance path.

Measuring NOR flash time-to-completion during reads detects threshold voltage dispersion shifts, enabling proactive data relocation before corruption occurs.

Multi-stage erase operations reduce trap-up effects by dynamically adjusting voltage offsets during distinct erasure phases.

Interleaving charge pumps segments charging cycles to lower peak current, preserving battery life in portable devices.

Applying dummy pulse initializes channel region after program loop, preventing threshold voltage sensing errors during read operation.

Selective row refresh reduces power consumption and processing time by skipping unused memory cells.

A reference voltage generator tracks threshold voltages to adjust bit line and word line voltages in memory arrays.

Distributed compaction narrows voltage distributions across memory cells, reducing program verify pulses and lowering power consumption.

A semiconductor device generates a chip-unique ID by extracting random bit errors from embedded memory using a variable power supply circuit.

Adjusting read voltages according to adjacent cell states reduces coupling-induced errors while maintaining high storage density in NAND flash devices.

Real-time feedback controls floating gate charge during Fowler-Nordheim tunneling, preventing over-programming and reducing conduction threshold dispersion.

Address final-cycle signal keeps input buffer active before chip determination, preventing data loss while reducing power consumption on non-target NAND chips.

A poly fuse burning system uses a controllable power source and monitor circuit to adjust voltage levels during the burning process.

Detecting defects in stacked memory cells during erase operations prevents reliability issues caused by narrow element intervals.

A bootstrap boosting circuit raises output potential through capacitive coupling to maintain high gate voltage levels.

Dynamic bit line precharge timing prevents channel boosting during incremental step pulse programming, maintaining efficiency across all program loops.

Asymmetric bit and source line paths maintain consistent total resistance across resistive memory cells.

Multiple redundant signal pathways provide access to an antifuse in a non-volatile memory cell, ensuring data availability when primary routes fail.

A page buffer circuit latches sensing values from adjacent and selected memory cells to improve data reading accuracy.

A sense amplifier circuit applies distinct read voltages to bit lines for current comparison.

Summing initial currents creates temperature-compensated references that resolve measurement precision issues in multilevel phase change memory cells.