Partial Bank Refresh for Memory Power Optimization
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Solution Overview
Problem
Conventional memory device refresh operations consume significant power by refreshing all memory cells, including unused or stale data, leading to inefficiency in power usage and processing time, especially in power-constrained systems like mobile devices.
Innovation Solution
Implementing partial memory bank refresh control that tracks utilized memory rows and only refreshes those, reducing the number of rows activated during each refresh operation and eliminating unnecessary refresh commands, thereby conserving power and IO bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory refresh operations are performed on all memory cells, then data retention is maintained, but power consumption increases significantly
Solution Approach 1:
The memory array is divided into multiple segments (e.g., quadrants, rows, or columns) with independent refresh control. The controller identifies and refreshes only the segments containing valid data,而非entire memory array. This segmentation allows selective refreshing that maintains data retention for used cells while skipping unused cells, directly resolving the contradiction between maintaining reliability and reducing power consumption.
Solution Approach 2:
Different refresh strategies are applied to different regions of the memory array based on local data validity. Regions with valid data receive full refresh operations, while regions with invalid or stale data receive reduced or no refresh operations. This local differentiation optimizes power consumption by concentrating refresh efforts only where needed, while maintaining data retention for critical regions.
2Reliability
If refresh operations are performed on all memory rows, then data integrity is maintained, but processing time increases
Solution Approach 1:
The refresh operation is segmented into multiple independent phases corresponding to different memory regions. The controller executes refresh operations on only those segments containing valid data, parallelizing the refresh process across multiple regions simultaneously. This reduces total processing time while maintaining data integrity in refreshed segments through coordinated refresh scheduling and timing.
Solution Approach 2:
Instead of performing complete refresh operations on all memory rows, the system applies partial refresh actions only to rows containing valid data. The controller identifies unused or stale data regions and excludes them from refresh operations, performing approximately the necessary refresh actions rather than exhaustive refresh of entire memory array, thereby reducing processing time while maintaining data integrity where required.
3Quantity of substance
If memory device operates at full capacity, then storage capability is maximized, but power consumption during refresh increases
Solution Approach 1:
The system maintains full memory storage capacity availability while applying localized refresh operations only to regions containing valid data. The controller tracks data validity status across different memory regions and dynamically adjusts refresh operations accordingly, allowing the memory device to operate at full storage capacity while minimizing refresh power consumption by concentrating refresh efforts only where data is actually stored.
Data Source
AI summary
Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.