eFuse OTP Memory With I2C Slave Interface
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Solution Overview
Problem
The implementation of eFuse OTP memory in custom ICs often faces issues with functional and electrical properties due to insufficient review of write/read functions during production, leading to defects and manufacturing challenges.
Innovation Solution
An eFuse OTP memory system that includes an I2C slave configured for I2C communication, with a register block, an eFuse controller, and clock control, enabling one-time writing and multiple readings across multiple addresses, and supporting data writing and reading through a serial clock and data line, thereby simplifying the integration and reducing design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an individual directly implements a control circuit for the eFuse, then the eFuse IP can be customized and integrated into custom IC design, but functional and electrical properties may have defects due to insufficient review of write/read functions during production
Solution Approach 1:
The patent introduces a standardized control circuit interface as an intermediary between the eFuse IP and the custom IC design. This intermediary provides a proven, pre-verified control mechanism that eliminates the need for individuals to directly implement control circuits, thereby ensuring reliable write/read functions while maintaining customization capability through the standardized interface.
2Reliability
If a standardized eFuse IP with control circuit is provided after silicon-proving, then reliability and manufacturing stability are improved, but product development time increases due to the silicon-proving process
Solution Approach 1:
The control circuit is silicon-proven and verified in advance before being integrated with the eFuse IP. This preliminary action ensures that the control mechanism is thoroughly tested and reliable before deployment, preventing defects from occurring during actual production while maintaining a streamlined integration process.
3Ease of manufacture
If the eFuse IP includes integrated control circuit, then ease of integration is improved, but device complexity increases due to additional control logic
Solution Approach 1:
The eFuse system is segmented into distinct functional modules: the eFuse IP core and the control circuit. This segmentation allows each module to be independently designed, verified, and optimized. The control circuit handles all complex control logic, while the eFuse IP focuses on its core function, thereby simplifying the overall integration process while managing complexity through modular architecture.
Data Source
AI summary
An eFuse one-time programmable (OTP) memory is provided. The eFuse OTP memory supports inter integrated circuit (I2C) communication, and an operation method thereof. The eFuse OTP memory includes: an eFuse intellectual property (IP) which data writes once and data reads multiple times for a plurality of addresses; and an I2C slave which communicates with an I2C master based on a serial clock line and a serial data line, and performs the data write and the data read to and from the eFuse IP.