Memory Array Insulative Tiers With Etch-Blocking Lines
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Solution Overview
Problem
Existing memory array technologies face challenges in reducing the risk of shorts between conductor tiers and conductive tiers during the manufacturing process of memory arrays with strings of memory cells.
Innovation Solution
The method involves forming a memory array with vertically-alternating conductive and insulative tiers, where horizontally-elongated lines of different composition are formed in the insulative tier above the conductive tiers. These lines help in reducing the risk of etching and subsequent shorts by blocking the etching action.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes are used for memory arrays, then manufacturing simplicity is maintained, but the risk of shorts between conductor tiers and conductive tiers increases
Solution Approach 1:
The patent applies preliminary action by forming protective lines in the insulative tier before etching the trenches. These lines are created in advance to block etching action and prevent shorts between conductor tiers and conductive tiers during subsequent manufacturing steps.
Solution Approach 2:
The patent uses horizontally-elongated lines as intermediary structures between the insulative tier and the trenches. These lines act as mediators that block the etching action, preventing direct contact between conductor tiers and conductive tiers, thus eliminating the short circuit risk.
2Reliability
If vertically-alternating conductive and insulative tiers are formed without protective lines, then manufacturing process is simpler, but electrical isolation between tiers is compromised
Solution Approach 1:
The patent segments the insulative tier by forming horizontally-elongated lines within it. These lines create distinct regions that provide electrical isolation between different conductor tiers, preventing shorts while maintaining the vertical stacking architecture.
Solution Approach 2:
The patent applies local quality by forming lines with different composition than the surrounding insulative material at specific locations. These locally-modified regions provide enhanced electrical isolation properties where needed, specifically at interfaces between conductor tiers and conductive tiers.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.