NAND Flash Memory Error Management via Adaptive ECC and Array Segmentation
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Solution Overview
Problem
Conventional error correction codes (ECC) in flash memory systems are resource-intensive and designed for worst-case error correction, leading to performance degradation and overhead, especially as the memory ages and error rates increase, necessitating a more efficient error management approach.
Innovation Solution
The implementation of a method that partitions the memory array into two portions, where high-density storage with a smaller margin of error is used for efficient data storage, and data is rewritten to a lower error-prone portion if excessive errors are detected, allowing for a smaller and more efficient ECC to be used, thereby improving performance and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction codes (ECC) are used for worst-case error correction, then reliability is improved, but device complexity and processing time increase
Solution Approach 1:
The patent segments the memory array into multiple portions with different error characteristics. By dividing the memory into distinct regions (e.g., first portion with higher error rate, second portion with lower error rate), the system can apply different ECC strategies to each segment, reducing the overall ECC complexity while maintaining reliability.
Solution Approach 2:
The patent applies local quality by using different error correction approaches for different memory portions. High-density storage portions with smaller error margins use adaptive error management, while other portions use conventional ECC. This localized differentiation reduces the need for complex worst-case ECC across the entire memory system.
2Productivity
If high-density storage is used, then productivity is improved, but manufacturing precision requirements increase due to smaller error margins
Solution Approach 1:
The patent implements dynamic error management where the system adaptively adjusts error correction strategies based on detected error rates in high-density storage portions. When excessive errors are detected, the system dynamically rewrites data to alternative portions, allowing high-density storage to be used without requiring extremely tight manufacturing precision.
Solution Approach 2:
The patent changes operational parameters by monitoring error rates and adapting the storage strategy accordingly. When error rates in high-density portions exceed thresholds, the system changes parameters by rewriting to different memory portions with different error characteristics, effectively managing the precision requirements.
3Reliability
If memory is rewritten to lower error-prone portions, then reliability is improved, but loss of time occurs due to additional write operations
Solution Approach 1:
The patent performs preliminary actions by proactively monitoring error rates in high-density storage portions and identifying suitable alternative portions before failures occur. By pre-positioning data in appropriate memory regions based on error characteristics, the system reduces the need for reactive rewrites, minimizing time loss while maintaining reliability.
Data Source
AI summary
Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.