Memory Controller Reliability Countermeasure Scheduler
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in optimizing the scheduling of reliability countermeasures for nonvolatile semiconductor memories, leading to unnecessary operations that increase load and decrease processing speed, thereby impairing reliability.
Innovation Solution
A memory system with a reliability countermeasure scheduler that tracks access processes and skips unnecessary countermeasures by using a time stamp table and bitmap to determine when the effects of previous operations are still valid, thereby optimizing the schedule of reliability countermeasures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reliability countermeasure processes are executed frequently, then reliability is improved, but processing speed deteriorates due to increased load
Solution Approach 1:
The reliability countermeasure scheduler skips unnecessary reliability countermeasure processes by determining whether previous operations' effects are still valid. When effects remain valid, the scheduler rushes through by skipping redundant operations, thereby reducing load and improving processing speed while maintaining necessary reliability checks.
Solution Approach 2:
The system performs preliminary tracking of operation effects using time stamp tables and bitmaps to determine future scheduling decisions. By preliminarily assessing whether previous operations' effects persist, the system avoids unnecessary subsequent operations, optimizing the balance between reliability and processing speed.
2Reliability
If reliability countermeasure processes are executed frequently, then reliability is improved, but productivity deteriorates due to increased load
Solution Approach 1:
The scheduler skips redundant reliability countermeasure processes by tracking whether previous operations' effects are still valid. This skipping mechanism reduces unnecessary load on memory cells and improves overall productivity while maintaining adequate reliability through selective execution of necessary countermeasures.
Solution Approach 2:
Instead of executing reliability countermeasures excessively or fully on all memory regions, the system applies partial action by selectively targeting only those regions where previous operation effects have expired. This optimized approach improves productivity by avoiding excessive unnecessary operations while maintaining reliability where needed.
3Speed
If access processes are increased to improve performance, then processing speed is improved, but reliability deteriorates due to excessive load on memory cells
Solution Approach 1:
The reliability countermeasure scheduler implements feedback by continuously monitoring the effects of previous access processes on memory cells. Based on this feedback regarding effect validity, the scheduler dynamically adjusts the execution of reliability countermeasures, ensuring adequate protection against excessive load while allowing high-performance access processes to proceed.
Data Source
AI summary
A memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller is configured to schedule plural types of reliability countermeasure processes to be executed for the nonvolatile semiconductor memory. The plural types of reliability countermeasure processes includes at least a first reliability countermeasure process. The memory controller is configured to skip the first reliability countermeasure process to be executed when the first reliability countermeasure process is not necessary to be executed by executing an access process other than the first reliability countermeasure process to the nonvolatile semiconductor memory.