Page Buffer Circuit Latching for Nonvolatile Memory Read Reliability
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Solution Overview
Problem
Nonvolatile memory devices face challenges in accurately reading data from memory cells due to interference from adjacent cells, leading to reduced reliability and increased area requirements.
Innovation Solution
A nonvolatile memory device with a memory cell array and a page buffer circuit that latches sensing values from both adjacent and selected memory cells multiple times, using a row decoder circuit to select word lines and bit lines, and a control logic circuit to manage voltages and sensing operations, improving data accuracy and reducing area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple sensing operations are performed to improve read accuracy, then data reading reliability is improved, but device complexity increases
Solution Approach 1:
The sensing operation is segmented into multiple distinct phases: first sensing operation to read data from first memory cells, and second sensing operation to read data from second memory cells. Each sensing operation uses dedicated word lines and is separated in time, allowing independent optimization of each sensing phase while maintaining overall reliability through multiple readings.
Solution Approach 2:
The first sensing operation is performed as a preliminary action before the second sensing operation. By conducting the first sensing operation on first memory cells first, the system establishes baseline data before proceeding to read from second memory cells, enabling comparative analysis and improving overall reading reliability through sequential preparation.
2Measurement precision
If multiple latches are used to store sensing values, then data accuracy is improved, but area increases
Solution Approach 1:
Multiple latches (first latches and second latches) are merged into a single integrated page buffer circuit structure that shares common word lines, bit lines, and control logic. The latches are positioned adjacent to each other within the same circuit block, allowing multiple sensing values to be stored in close proximity without requiring separate dedicated storage regions, thus improving accuracy while minimizing area increase.
Solution Approach 2:
The page buffer circuit is designed as a universal structure that serves multiple functions: it stores sensing values from both first and second memory cells, provides multiple latches for redundant storage, and shares common access pathways through word lines and bit lines. This multi-functional design allows the circuit to maintain high data accuracy through multiple storage locations while avoiding the area penalty of completely separate storage systems.
3Reliability
If adjacent memory cells are read first, then interference effects are reduced, but operation time increases
Solution Approach 1:
The reading operation is segmented into distinct temporal phases where first memory cells are read during a first time interval, and second memory cells are read during a second time interval. This segmentation prevents temporal overlap and interference between adjacent cell readings, improving reliability while managing time through structured sequencing rather than simultaneous operations.
Solution Approach 2:
The first sensing operation on first memory cells is performed as a preliminary action before the second sensing operation on second memory cells. By completing the first sensing operation in advance, the system establishes accurate baseline readings before proceeding to adjacent cells, reducing interference effects through temporal separation while optimizing the overall time sequence to minimize total reading duration.
Data Source
AI summary
Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.