Dynamic Select Gate Scan Prioritization for Memory Sub-systems
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Solution Overview
Problem
Existing memory sub-systems face increased latency and decreased quality of service due to the static nature of select gate scan operations, which fail to account for variations in quality characteristics across memory dice, leading to charge loss and voltage drift phenomena.
Innovation Solution
Implementing adaptive select gate scan operations that determine and prioritize scan operations based on quality characteristics such as fuse_ID, program-erase cycles, operating temperatures, and physical age, by modulating scan voltages and using a dynamic read level and one check fail byte scheme to identify degradation in select gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static select gate scan operations are performed on all memory dice uniformly, then comprehensive monitoring is achieved, but latency increases and quality of service decreases
Solution Approach 1:
The patent applies local quality by differentiating scan operations based on individual memory die characteristics. Each memory die receives scan operations tailored to its specific quality attributes (fuse_ID, program-erase cycle count, operating temperature history, physical age), rather than applying a uniform scan regime to all dice. This allows critical memory dice to be monitored more frequently while less critical dice receive reduced scanning, resolving the contradiction between comprehensive monitoring and latency reduction.
Solution Approach 2:
The patent implements dynamic scan prioritization where the scan frequency and intensity for each memory die are adjusted based on real-time quality characteristics. The system continuously evaluates attributes such as program-erase cycle counts and operating temperatures to dynamically reprioritize scan operations. This dynamic approach allows the system to adapt monitoring resources to actual needs, reducing unnecessary scans on stable memory dice while intensifying monitoring on degrading dice, thereby reducing overall latency while maintaining reliability.
2Device complexity
If uniform scan frequency is applied to all memory dice, then simple control is maintained, but charge loss and voltage drift phenomena occur due to inability to account for quality variations
Solution Approach 1:
The patent addresses charge retention issues by applying local quality principles to scan operations. Each memory die is evaluated based on its specific quality characteristics including fuse_ID, program-erase cycle history, operating temperature exposure, and physical age. Memory dice exhibiting signs of degradation or higher risk factors receive intensified scan operations to detect and correct charge loss and voltage drift phenomena, while stable memory dice maintain standard scanning. This targeted approach ensures reliable charge retention monitoring without requiring complex uniform control across all dice.
Solution Approach 2:
The patent implements feedback mechanisms where scan results and quality characteristic measurements inform future scan prioritization decisions. The system monitors charge retention status, program-erase cycle counts, and operating conditions, then uses this feedback to adjust scan frequency and intensity for individual memory dice. This feedback loop enables the system to proactively address charge loss and voltage drift by increasing scan operations on memory dice showing degradation signs, while maintaining simple control through automated decision-making algorithms.
3Loss of time
If selective scan operations are implemented based on quality characteristics, then latency is reduced and quality of service improves, but system complexity increases
Solution Approach 1:
The patent manages system complexity through dynamic prioritization algorithms that automatically adjust scan operations based on real-time quality characteristics. The system evaluates multiple parameters (fuse_ID, program-erase cycles, operating temperature, physical age) and dynamically reprioritizes scan tasks without requiring complex manual intervention. This dynamic approach reduces latency by focusing scan operations on critical memory dice while maintaining manageable system complexity through automated decision-making and adaptive resource allocation.
Solution Approach 2:
The patent handles increased system complexity by changing operational parameters rather than fundamental architecture. The system adjusts scan frequency, scan voltage levels, and prioritization weights based on measured quality parameters. By modifying operational parameters dynamically rather than redesigning the core scan architecture, the patent achieves reduced latency and improved quality of service while keeping system complexity increases minimal and manageable through parameter-based control.
Data Source
AI summary
Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.