Configurable Page Size in NAND Flash Memory Banks
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Solution Overview
Problem
NAND flash memory architectures face performance and reliability issues in applications with small file sizes, as they require frequent erase and program cycles, leading to reduced endurance and high power consumption due to the need to modify entire memory blocks, even when only a small portion of the data is updated.
Innovation Solution
A flash memory device with a configurable page size, allowing any combination of planes to be accessed simultaneously, enabling flexible page size configuration during operations, which reduces unnecessary erase and program cycles and improves system performance by allowing dynamic configuration of page size based on the specific operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire memory block is erased and reprogrammed for small data updates, then data integrity is maintained, but power consumption increases and endurance decreases
Solution Approach 1:
The memory block is segmented into multiple planes, and the patent enables selective erasure and programming of only the necessary planes containing updated data. This segmentation allows small data updates to affect only specific planes rather than requiring erasure of the entire block, thereby reducing power consumption while maintaining data integrity in the updated portions.
Solution Approach 2:
The patent introduces dynamic configuration of page size and selective plane access based on the actual data update requirements. The system can dynamically adjust which planes are accessed during erase and program operations, adapting to the specific needs of each update operation rather than following a fixed block-level approach.
2Reliability
If the entire memory block is erased and reprogrammed for small data updates, then data consistency is ensured, but program-erase cycle count increases reducing endurance
Solution Approach 1:
By dividing the memory block into multiple planes and enabling selective access to individual planes, the patent reduces the number of program-erase cycles required. Only the planes containing updated data undergo erasure and programming, while other planes remain intact, thereby extending the overall endurance of the memory device.
Solution Approach 2:
The patent applies local quality by treating different planes differently based on their update status. Planes requiring updates receive full erase and program treatment, while planes without updates are left unchanged, optimizing the use of program-erase cycles and improving endurance.
3Device complexity
If fixed page size is used in NAND flash memory, then device structure is simplified, but performance degrades for applications with varying file sizes
Solution Approach 1:
The patent implements dynamic page size configuration by allowing the system to select different page sizes based on the specific operation and data requirements. This dynamic approach enables the memory device to optimize performance for different file sizes and access patterns without requiring multiple fixed configurations, thereby improving productivity while maintaining manageable device complexity.
Solution Approach 2:
The patent changes the page size parameter dynamically based on operational needs. By allowing the page size to vary according to the specific access pattern and data size, the system can optimize performance for different applications without significantly increasing device complexity.
4Productivity
If multiple planes are accessed simultaneously with configurable page size, then handling efficiency for small files improves, but control circuit complexity increases
Solution Approach 1:
The patent segments the memory into multiple planes that can be independently controlled and accessed. This segmentation allows efficient handling of small files by accessing only the necessary planes, improving productivity while distributing the control complexity across multiple manageable plane controllers.
Data Source
AI summary
A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.