Memory System Program Speed-Based Page Ordering
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Solution Overview
Problem
Current semiconductor memory systems face reliability issues due to variations in program speeds across memory cells, leading to disturbances in threshold voltage distributions during programming operations.
Innovation Solution
A memory system that measures program speeds of each page in a memory cell array and adjusts the programming order based on this information, prioritizing slower cells to optimize threshold voltage distribution and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pages are programmed in sequential order, then the programming process is simple, but threshold voltage distribution disturbances occur due to program speed variations
Solution Approach 1:
The patent applies preliminary action by measuring and storing program speed information for each page before actual programming operations. The controller pre-establishes a mapping between physical block addresses and pages based on their program speeds, so that when programming is needed, the optimal sequence is already determined without requiring complex real-time adjustments during the programming process itself.
Solution Approach 2:
The patent implements dynamics by making the programming sequence adaptable rather than fixed. The controller dynamically adjusts the programming order based on the stored program speed information, selecting pages with slower program speeds to be programmed first. This dynamic adaptation allows the system to optimize threshold voltage distribution while maintaining relatively simple control logic.
2Reliability
If pages are programmed based on program speed information, then reliability is improved, but additional measurement and storage operations are required
Solution Approach 1:
The patent performs the time-consuming program speed measurement and storage operations as preliminary actions during manufacturing or initial system setup. By establishing the program speed information and address mapping in advance, the system avoids repeating these measurements during normal operation, thus minimizing the time loss while ensuring reliable programming sequences during actual use.
3Reliability
If sequential address mapping is used, then address management is simple, but program speed variations cause threshold voltage disturbances
Solution Approach 1:
The patent resolves this contradiction by pre-establishing an optimized address mapping that accounts for program speed variations. The controller stores the relationship between physical block addresses and pages in a predetermined order based on program speeds, allowing the system to maintain simple address management during operation while avoiding threshold voltage disturbances through the pre-planned mapping strategy.
Data Source
AI summary
There are provided a memory system having improved reliability and an operating method thereof. A memory system includes a semiconductor memory device including a memory cell array having a plurality of pages, and a controller for sequentially transmitting, to the semiconductor memory device, physical block addresses of pages to be programmed among the plurality of pages. In the memory system, the semiconductor memory device selects a page corresponding to each of the physical block addresses among the plurality of pages according to previously stored program speed information, and performs a program operation on the selected page.