Chip-Unique ID Generation Using Embedded Memory Bit Errors
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Solution Overview
Problem
Existing methods for generating a chip-unique ID in semiconductor devices require dedicated processes and hard macros, increasing costs and area overhead, while also being vulnerable to data falsification and limited bit length.
Innovation Solution
A semiconductor device that utilizes bit errors in on-chip embedded memory at random addresses to generate a chip-unique ID, employing a variable power supply circuit and test circuit to extract error data, thereby eliminating the need for dedicated hard macros and allowing for longer bit lengths without area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated processes and hard macros are used for generating chip-unique ID, then ID generation capability is achieved, but manufacturing cost and area overhead increase
Solution Approach 1:
The patent applies universality by making the embedded memory serve dual purposes: it functions as both the storage medium for data and as the source for generating chip-unique ID. By utilizing bit errors that naturally occur in memory cells at random addresses, the system eliminates the need for dedicated hard macros, thereby reducing area overhead while maintaining ID generation capability.
Solution Approach 2:
The patent implements self-service by allowing the memory system to generate its own unique identifier through inherent bit errors. The test circuit automatically detects these errors and uses them to create the chip-unique ID without requiring external dedicated processes, thus simplifying the manufacturing process and reducing costs.
2Reliability
If dedicated hard macro is used for ID generation, then ID generation is enabled, but bit length is limited
Solution Approach 1:
The patent applies dynamics by making the chip-unique ID length flexible and adaptable. Since the ID is generated from bit errors in embedded memory, the length can be adjusted based on the memory size and error distribution, allowing for longer bit lengths compared to fixed dedicated hard macro implementations.
3Reliability
If data is written at manufacturing using dedicated processes, then ID is stored, but risk of data falsification increases
Solution Approach 1:
The patent converts the harmful aspect of bit errors (which are typically considered defects) into a beneficial feature for security. By using these random bit errors as the basis for generating the chip-unique ID, the system creates an identifier that is inherently difficult to falsify, as reproducing the exact same error pattern would be extremely difficult.
4Device complexity
If existing memory is used for ID generation, then area overhead is reduced, but verification complexity increases
Solution Approach 1:
The patent introduces a test circuit as an intermediary component that simplifies the verification process. This test circuit automatically detects bit errors in the embedded memory and generates the chip-unique ID, thereby reducing verification complexity despite using existing memory for ID generation.
Data Source
AI summary
By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.