Shared Address Counting Circuit for Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor devices face challenges in improving performance due to inefficiencies in the design of address counting circuits, which are crucial for managing column addresses across multiple memory banks, leading to increased circuit area and complexity.
Innovation Solution
The implementation of a shared address counting circuit that generates first and second shared addresses at the edges of a counting clock signal, combined with a latch circuit to produce column addresses using latch clock signals, efficiently manages addresses and reduces circuit area by sharing weights and counters across memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate address counting circuit is designed for each memory bank, then each bank can independently manage its column addresses, but the circuit area and system complexity increase significantly
Solution Approach 1:
The patent merges the address counting functionality into a single shared circuit that serves multiple memory banks. The address counting circuit generates a shared address that is common to all banks, eliminating the need for separate counting circuits in each bank while maintaining independent address management through bank-specific latch circuits.
Solution Approach 2:
The address counting circuit is designed with universal functionality to serve multiple memory banks simultaneously. It generates a shared address that can be latched and used by any number of banks, making the counting circuit multi-functional rather than dedicated to a single bank.
2Reliability
If multiple independent address counting circuits are used for multiple memory banks, then each bank has dedicated address control, but the overall circuit area increases
Solution Approach 1:
The patent combines the address counting functionality into a single shared circuit located in the column address control unit. This shared counting circuit generates addresses that are then distributed to multiple banks through individual latch circuits, significantly reducing the total circuit area compared to having separate counting circuits in each bank.
Solution Approach 2:
The patent introduces a shared address as an intermediary element between the single address counting circuit and multiple memory banks. This shared address acts as a mediator that carries the counted address information from the common counting circuit to the various banks, enabling area-efficient address distribution.
3Area of stationary object
If a shared address counting circuit is used for multiple memory banks, then circuit area is reduced, but address generation timing becomes more complex
Solution Approach 1:
The patent segments the address generation process into two distinct phases: counting phase and latching phase. The shared address counting circuit operates during the counting phase to generate the shared address, while bank-specific latch circuits operate during the latching phase to capture and hold the address for individual banks. This segmentation simplifies timing control by separating the complex operations into manageable stages.
Solution Approach 2:
The address counting circuit performs preliminary action by generating the shared address in advance before it is latched by the individual bank latch circuits. This preliminary generation of the shared address allows the timing control to be simplified, as the address data is prepared and available for latching without requiring complex real-time coordination during the latching operation.
Data Source
AI summary
An address counting circuit includes a shared address counting circuit configured to generate a first shared address and a second shared address by counting an external start address at a first edge and a second edge of a counting clock signal and a latch circuit including a plurality of latches configured to share the first shared address and the second shared address, respectively and generate a plurality of column addresses by latching the first shared address and second shared address according to a plurality of latch clock signals.