Multi-Stage Erase Operation for Non-Volatile Memory Endurance
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Solution Overview
Problem
Non-volatile memory devices face issues such as 'program disturb' and 'trap-up' effects during erase operations, which limit the number of program/erase cycles and affect the endurance and reliability of memory cells.
Innovation Solution
A multi-stage erase operation is implemented, where voltages applied to the GIDL generator and select gate devices are ramped up and reduced in a controlled manner to minimize electrostatic fields and reduce electron trapping, allowing for increased endurance without adding new components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-stage erase operation is used, then the erase speed is fast, but trap-up effects occur and electron trapping increases, reducing memory endurance
Solution Approach 1:
The erase operation is divided into multiple stages with different voltage profiles. The first stage uses a first voltage profile to perform initial erasure, while the second stage uses a second voltage profile to complete the erasure and reduce trap-up effects. This segmentation allows optimization of each stage for specific purposes, improving overall reliability without significantly compromising total erase speed.
Solution Approach 2:
The voltage applied to the GIDL generator and select gate devices is dynamically adjusted between stages. During the first stage, voltages are set to enable efficient erasure, while in the second stage, voltages are modified to minimize electron trapping and reduce trap-up effects on non-selected cells. This dynamic voltage adjustment resolves the contradiction between speed and reliability.
2Reliability
If higher threshold voltages are applied to select gate devices to improve selectivity, then program disturb effects increase and electron trapping worsens, but if lower voltages are used, selectivity decreases
Solution Approach 1:
The select gate device voltages are dynamically adjusted between the two erase stages. In the first stage, higher voltages provide good selectivity, while in the second stage, voltages are optimized to reduce program disturb effects and electron trapping. This temporal variation in voltage levels resolves the contradiction between selectivity and harmful effects.
Solution Approach 2:
The erase operation uses periodic voltage application with distinct patterns for each stage. The voltage waveform is designed to alternate between different amplitude levels, providing high selectivity during the first period and reduced stress during the second period, thereby eliminating program disturb and trap-up effects while maintaining selectivity.
3Productivity
If more program/erase cycles are performed to increase memory utilization, then trap-up effects accumulate and reduce the number of remaining cycles the memory can endure
Solution Approach 1:
The second erase stage acts as a preliminary conditioning step that reduces electron trapping and mitigates trap-up effects before the memory undergoes subsequent program/erase cycles. By performing this protective action during each erase operation, the memory can sustain more total cycles, increasing overall utilization while preserving endurance.
Solution Approach 2:
The multi-stage erase operation provides beforehand cushioning by reducing trap-up effects and electron trapping during the erase process itself. This protective mechanism cushions the memory cells against the cumulative damage that would otherwise accumulate with repeated cycling, enabling higher memory utilization without compromising long-term reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-stage erase operation improves the reliability of memory devices by reducing trap-up effects and allowing higher threshold voltages for select gate devices, enhancing the overall endurance and performance of memory cells.
Implementation Method 1
causes a first voltage to be applied to a GIDL generator device at a source-end of the string of memory cells
Data Source
AI summary
Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset.