Flash Memory Bit State Assignment to Reduce Signal Coupling
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Solution Overview
Problem
In flash memory devices, especially multi-level cells, signal coupling between adjacent components leads to spurious signals and data storage errors due to increasing component density, causing floating gate-to-floating gate coupling and program disturb effects, which are exacerbated by higher programming voltages.
Innovation Solution
The control logic unit dynamically reassigned bit states on a row-by-row basis to minimize the application of higher programming voltages, by assigning the erased state to the largest number of cells, the lowest charge level to the second largest, the next level to the third largest, and the highest charge level to the smallest, thereby reducing floating gate-to-floating gate coupling and program disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If component density is increased to improve storage capacity, then storage capacity is improved, but signal coupling between adjacent components increases causing spurious signals and data storage errors
Solution Approach 1:
The patent applies local quality by assigning different bit state mappings to different rows of memory cells. Specifically, even rows use one mapping (e.g., 00=erased, 01=level1, 10=level2, 11=level3) while odd rows use an inverted mapping (e.g., 00=erased, 01=level3, 10=level2, 11=level1). This local differentiation reduces signal coupling effects between adjacent cells by varying the charge distribution patterns across rows.
2Speed
If higher programming voltages are applied to program memory cells, then programming speed is improved, but floating gate-to-floating gate coupling and program disturb effects are exacerbated
Solution Approach 1:
The patent changes the parameter of bit state assignment to minimize the need for high programming voltages. By strategically mapping bit states to charge levels such that frequently accessed or adjacent cells use charge levels that minimize coupling, the system can achieve reliable programming at lower voltages, thereby reducing program disturb effects while maintaining acceptable programming speeds.
3Productivity
If bit states are assigned to maximize storage efficiency, then storage efficiency is improved, but floating gate-to-floating gate coupling increases reducing data storage accuracy
Solution Approach 1:
The patent introduces dynamic bit state assignment where the mapping between bit states and charge levels varies by row parity. This dynamic approach allows the system to optimize for both storage efficiency and accuracy simultaneously - full utilization of charge levels is maintained while the alternating pattern prevents systematic coupling errors that would occur with a static uniform assignment across all rows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the occurrence of floating gate-to-floating gate coupling and program disturb effects by optimizing bit state assignments, reducing the need for high programming voltages and thus enhancing data storage accuracy and reliability in flash memory devices.
Implementation Method 1
A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the channel region by a layer of gate oxide. A control gate is fabricated over the floating gate, and it can also be made of doped polysilicon. The control gate is electrically separated from the floating gate by a dielectric layer.
Implementation Method 2
For example, a negative charge can be placed on the floating gate by grounding the source while applying a sufficiently large positive voltage to the control gate to attract electrons, which tunnel through the gate oxide to the floating gate from the channel region.
Implementation Method 3
The amount of charge stored on the flash memory cell determines the magnitude of the threshold voltage that must be applied to the control gate to allow the flash memory cell to conduct current between the source and the drain. As negative charge is added to the floating gate, the threshold voltage of the flash memory cell increases.
Implementation Method 4
The cell can be erased by applying a gate-to-source voltage to the cell that has a polarity opposite that used for programming. Specifically, the control gate is grounded, and a large positive voltage is applied to the source to cause the electrons to tunnel through the gate oxide and deplete the charge from the floating gate.
Data Source
AI summary
A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row.