Dynamic Verification Start Loops for Memory Programming Efficiency
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently programming memory cells due to varying program speeds across different word lines, which can lead to prolonged programming times and inefficiencies, especially after a large number of program-erase cycles, as fixed verification start loops may not adapt to changing program speeds.
Innovation Solution
The semiconductor memory device employs a peripheral circuitry that determines and adjusts verification start loops based on sensing results during program-verify loops, allowing for dynamic adjustment of program-verify loops for each word line group, thereby optimizing programming efficiency by counting turn-on memory cells and comparing them to thresholds to determine optimal loop points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed verification start loops are used for programming memory cells, then the programming process is simple and consistent, but programming time increases and efficiency decreases due to varying program speeds across different word lines
Solution Approach 1:
The patent implements dynamic adjustment of verification start loops based on actual sensing results during program-verify loops. Instead of using fixed verification start loops, the system determines optimal verification start loops in real-time by monitoring turn-on memory cell counts and comparing them to thresholds. This dynamic approach adapts to varying program speeds across different word lines and program-erase cycles, resolving the contradiction between maintaining simple fixed procedures and achieving high programming efficiency.
Solution Approach 2:
The patent incorporates feedback mechanisms where sensing results from program-verify loops are continuously monitored and used to adjust subsequent programming operations. The system counts turn-on memory cells during verification, compares counts to thresholds, and uses this feedback to determine optimal verification start loops for future operations. This feedback loop enables the system to adapt to changing program speeds while maintaining efficient programming, addressing the contradiction between simplicity and efficiency.
2Loss of time
If dynamic adjustment of verification start loops is implemented, then programming time is reduced and efficiency is improved, but the complexity of programming control increases
Solution Approach 1:
The patent segments the programming control process into distinct functional modules: counting circuits that monitor turn-on memory cells, comparison circuits that evaluate counts against thresholds, and control circuits that determine verification start loops based on comparison results. This segmentation breaks down the complex dynamic adjustment process into manageable, independent components, reducing overall system complexity while enabling time-efficient programming through adaptive verification start loop selection.
Solution Approach 2:
The programming system performs self-adjustment by automatically determining optimal verification start loops based on its own sensing results without requiring external intervention. The counting and comparison circuits use real-time feedback from the programming process itself to autonomously optimize subsequent operations, reducing programming time while keeping the control mechanism relatively simple through self-service adaptation.
Data Source
AI summary
A semiconductor memory device includes a memory cell array and peripheral circuitry. The memory cell array includes a block of memory cells The peripheral circuitry can perform first program-verify loops in response to a first write operation to a first word line in a word line group to program memory cells associated with the first word line to multiple states. The word line group includes one or more word lines. Then, the peripheral circuitry determines verification start loops of the multiple states based on sensing results in the first program-verify loops, and performs second program-verify loops with the determined verification start loops of the multiple states in response to a second write operation to a second word line in the word line group.