Resistive Memory Cell Wiring Asymmetry for Parasitic Resistance
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Solution Overview
Problem
Conventional resistive memory devices face challenges in maintaining high integration and low voltage operation due to parasitic resistances, which vary significantly across memory cells, requiring higher lithography and processing costs for miniaturization and integration.
Innovation Solution
The design includes a semiconductor device with a bit line and source line configuration where the electrical path from each memory cell to the bit line driver increases as the path to the source line driver decreases, maintaining consistent line resistance and reducing parasitic resistance effects, allowing for low-voltage operation and high integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are arranged in a conventional layout with uniform electrical paths, then manufacturing is simpler, but parasitic resistance varies significantly across memory cells requiring higher sensing margins and complicating operation
Solution Approach 1:
The patent applies asymmetry by intentionally designing different electrical path lengths for bit lines and source lines. Specifically, memory cells in rows have longer bit line paths but shorter source line paths, while memory cells in columns have shorter bit line paths but longer source line paths. This asymmetric design compensates for parasitic resistance variations, ensuring that the sum of bit line and source line resistances remains relatively constant across all memory cells, thereby improving sensing margin without requiring complex compensation circuits.
2Productivity
If lithography technology is advanced to achieve pattern miniaturization for higher integration, then device integration increases, but processing costs and manufacturing complexity increase
Solution Approach 1:
The patent changes the electrical path length parameter of bit lines and source lines to achieve high integration without requiring advanced lithography. By optimizing the electrical path lengths asymmetrically, the design achieves uniform total resistance across memory cells, improving reliability and allowing standard manufacturing processes to be used effectively. This parameter optimization enables higher integration densities while maintaining compatibility with existing manufacturing capabilities.
Data Source
AI summary
A resistive memory device resistive memory device includes a bit line configured to be driven by a bit line driver, a source line configured to be driven by a source line driver adjacent to the bit line driver, and a plurality of memory cells connected between the bit line and the source line. An electrical path of the bit line from each of the plurality of memory cells to the bit line driver increases as an electrical path of the source line from each of the plurality of memory cells to the source line driver decreases.