Current Sensing for Negative Threshold Voltage in NAND Flash
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Solution Overview
Problem
Current methodologies for sensing negative threshold voltage states in non-volatile storage devices, such as NAND flash memory, are inefficient due to long voltage sensing times and unsuitability for all bit line sensing, which is essential for concurrent sensing of multiple storage elements.
Innovation Solution
The method involves regulating the source and p-well voltages to a fixed, positive DC level during sensing, allowing for current sensing that avoids the disadvantages of voltage sensing, including ground bounce and the need for additional circuitry, enabling accurate sensing of negative threshold voltage states across all bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage sensing methodology is used for sensing negative threshold voltage states, then sensing can be performed, but the sense time becomes excessively long and it is unsuitable for all bit line sensing
Solution Approach 1:
The patent replaces voltage sensing with current sensing methodology. Instead of measuring voltage directly at the bit line, the invention senses current flowing through the storage element, which indirectly indicates the threshold voltage state. This substitution of measurement approach (from voltage to current) enables faster sensing speeds while maintaining accuracy for negative threshold voltage states
Solution Approach 2:
The invention changes the sensing parameter from voltage to current. By applying a fixed voltage to the bit line and measuring the resulting current through the storage element, the system achieves faster response times. The current sensing approach naturally provides faster rise times and eliminates the timing issues associated with voltage sensing methodologies
2Measurement precision
If voltage sensing is used, then sensing operation can be performed, but ground bounce occurs and additional circuitry is required
Solution Approach 1:
The patent substitutes current sensing for voltage sensing, which eliminates ground bounce issues. By measuring current through the storage element rather than voltage at the bit line, the invention avoids the ground reference problems that plague voltage sensing methodologies, simplifying the overall circuit design
Solution Approach 2:
The current sensing methodology uses the storage element itself as part of the sensing circuit. The storage element's current characteristics directly provide the sensing signal, eliminating the need for separate sense amplifiers and additional circuitry that would be required for voltage sensing approaches
3Productivity
If all bit line sensing is implemented for concurrent sensing of multiple storage elements, then productivity improves, but the complexity of ensuring accurate sensing across all bit lines increases
Solution Approach 1:
The patent implements a universal current sensing methodology that can be applied to all bit lines simultaneously. By using the same current sensing approach for every bit line in the array, the invention achieves concurrent sensing of multiple storage elements without requiring different sensing circuits for different bit lines, thereby maintaining simplicity while enabling high productivity
Solution Approach 2:
The invention segments the sensing operation by dedicating separate current sensing circuits to different bit line groups, allowing concurrent operation. This segmentation enables parallel sensing across multiple bit lines while maintaining the simplicity of individual current sensing stages, resolving the contradiction between productivity and complexity
Data Source
AI summary
Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.