Distributed Compaction of Logical States in Memory Arrays
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Solution Overview
Problem
The existing memory sub-systems face inefficiencies in programming time due to wider voltage distributions of logical states, which require multiple program verify pulses, increasing program time and power consumption.
Innovation Solution
The implementation of distributed compaction techniques, such as folding and selective slow program convergence, to narrow voltage distributions, reducing the need for program verify operations and associated power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If distributed compaction techniques are implemented to narrow voltage distributions, then program time is reduced and power consumption is lowered, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the voltage distribution compaction into distributed segments across multiple memory cells. Instead of uniformly compacting all voltage distributions, the system selectively applies compaction to specific segments where voltage distributions are wider than a threshold, thereby reducing program time for critical segments while maintaining overall system manageability.
Solution Approach 2:
The patent implements local quality by applying different compaction strategies to different regions of the voltage distribution based on local characteristics. The system monitors voltage distribution width at various points and applies compaction only where needed (where width exceeds threshold), rather than uniformly across all distributions, optimizing the balance between program time reduction and device complexity.
2Loss of energy
If distributed compaction techniques are implemented to narrow voltage distributions, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies partial action by implementing compaction only when voltage distribution width exceeds a defined threshold, rather than continuously or universally. This selective approach reduces power consumption by avoiding unnecessary compaction operations while still achieving energy savings in cases where it is beneficial, thereby balancing power reduction with acceptable device complexity.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the voltage distribution width parameter based on monitored conditions. When the width parameter exceeds a threshold, compaction is triggered to narrow the distribution; when it remains within acceptable limits, compaction is avoided. This parameter-driven approach optimizes power consumption while managing device complexity through conditional operation.
3Manufacturing precision
If multiple program verify pulses are used to verify wider voltage distributions, then programming accuracy is maintained, but program time increases
Solution Approach 1:
The patent applies preliminary action by proactively narrowing voltage distributions through distributed compaction before the verify operation is needed. By pre-reducing the voltage distribution width to within acceptable thresholds, the system ensures that subsequent verify operations require fewer pulses, thereby maintaining programming accuracy while significantly reducing the time spent on verification.
Solution Approach 2:
The patent implements skipping by eliminating unnecessary verify pulses through prior compaction. When voltage distributions are narrowed in advance through distributed compaction, the system can skip redundant verify operations that would otherwise be required for wider distributions, thus maintaining accuracy while accelerating the overall programming process.
Data Source
AI summary
A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.