3D Flash Memory Soft Program Speed via Static Substrate Biasing
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Solution Overview
Problem
In three-dimensional memory devices, parasitic capacitances between transistor well regions and substrates lead to prolonged soft program and verify operations due to the need for voltage switching, reducing efficiency and causing unnecessary power consumption.
Innovation Solution
A memory device design where the substrates of transistors in the word line driver and bit line switches maintain constant static voltages during soft program and verify operations, eliminating the need for voltage stabilization time and reducing parasitic capacitance charging/discharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage switching operations are performed on transistor substrates for different voltages required by soft program and verify operations, then the memory device can perform soft program and verify operations, but the operation time is prolonged and work efficiency is reduced
Solution Approach 1:
The patent divides the substrate voltage control into separate segments: the first substrate receives a first voltage, the second substrate receives a second voltage, and the third substrate receives a third voltage. This segmentation allows each substrate to be independently controlled, eliminating the need for repeated voltage switching and stabilization operations, thereby improving work efficiency while maintaining soft program and verify operation capability.
2Reliability
If voltage switching operations are performed on transistor substrates, then soft program and verify operations can be executed, but additional stabilization time is required which prolongs operation time
Solution Approach 1:
The patent applies preliminary action by pre-establishing the voltage distribution across the three substrates before the soft program and verify operations begin. The first substrate is pre-configured with the first voltage, the second substrate with the second voltage, and the third substrate with the third voltage. This preliminary voltage configuration eliminates the need for voltage stabilization time during the actual operations, significantly reducing the total operation time while ensuring reliable execution.
3Reliability
If repeated charging and discharging of parasitic circuits occurs during voltage switching, then voltage control for different operations is achieved, but unnecessary power consumption increases
Solution Approach 1:
The patent applies local quality by assigning different voltage characteristics to different substrates based on their specific functional requirements. The first substrate receives a first voltage optimized for word line driver operation, the second substrate receives a second voltage for complementary transistor operation, and the third substrate receives a third voltage for bit line switch operation. This localized voltage optimization eliminates unnecessary charging and discharging of parasitic circuits, reducing power consumption while maintaining precise voltage control capability.
Data Source
AI summary
A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.