NAND Flash Memory Edge Word Line Programming for Read Disturbance
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Solution Overview
Problem
NAND flash memory devices experience read disturbance issues due to biasing schemes during read operations, affecting the threshold voltages of memory cells, particularly those near edge word lines.
Innovation Solution
A method and circuit for programming memory cells in a memory array where edge word lines are programmed to a specific threshold voltage level, and selected cells between these edges are programmed according to input data, ensuring balanced voltage levels to prevent read disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional biasing schemes are applied during read operations, then read operation speed is maintained, but read disturbance occurs affecting threshold voltage stability
Solution Approach 1:
The patent applies preliminary action by programming edge word lines before normal read operations to establish a protective voltage pattern. This pre-programming creates a stable voltage distribution at the edges of the memory array that prevents read disturbance from propagating into adjacent memory cells during subsequent read operations.
Solution Approach 2:
The patent implements local quality by applying different programming states to different regions of the memory array. Specifically, edge word lines are programmed to a specific state (all 0s or all 1s) while internal word lines maintain their data-dependent states. This localized differentiation creates a protective buffer zone that stabilizes threshold voltages in nearby memory cells.
2Quantity of substance
If all memory cells are programmed according to input data, then data storage capacity is maximized, but read disturbance affects edge-adjacent cells
Solution Approach 1:
The patent applies segmentation by dividing the memory array into distinct regions: edge word lines and internal word lines. Edge word lines are segmented and programmed to uniform states independent of input data, while internal word lines retain data-dependent programming. This segmentation allows the system to maintain full data storage capacity in internal regions while protecting edge-adjacent cells from read disturbance.
3Reliability
If edge word lines are not programmed to specific threshold voltage levels, then programming time is reduced, but read disturbance cannot be suppressed
Solution Approach 1:
The patent implements partial action by programming only the necessary edge word lines to uniform states rather than re-programming the entire memory array. This selective programming of edge regions provides sufficient protection against read disturbance while minimizing the time and energy expenditure compared to comprehensive re-programming operations.
Data Source
AI summary
A method of operating a memory array is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns, wherein a plurality of parallel memory strings correspond to respective ones of the columns, and a plurality of word lines are arranged orthogonal to the plurality of memory strings, each word line being connected to gate electrodes of a corresponding one of the rows of memory cells. The method includes performing a program operation that programs all of the memory cells on edge word lines located at opposite edges of the memory array, and that programs selected memory cells between the edge word lines in the memory array according to input data to be stored in the memory array. Each programmed memory cell has a threshold voltage at a program verify (PV) level.