Non-Volatile Memory Array Two-Phase Programming Buffer Reduction

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Solution Overview

Problem

Multi-level programming in non-volatile memory (NVM) devices faces challenges due to the sensitivity of threshold voltage measurements, leading to erroneous results and inefficiencies in programming and erasing operations, particularly with the need for multiple buffers and phases to ensure uniform programming across memory cells.

Innovation Solution

A method is introduced that uses a two-phase programming approach with a first buffer for user data and a second buffer for programming and verification, where data is modified and refreshed between phases to ensure accurate programming of NVM cells, and data scrambling is employed to maintain uniform programming rates, all while reducing the number of required buffers for improved performance and die size savings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-level programming is used to increase storage capacity, then the amount of data stored per cell increases, but measurement precision deteriorates due to sensitivity of threshold voltage measurements

Engineering Contradiction:
Improvedata storage capacityVSAvoidthreshold voltage measurement accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The programming operation is divided into two distinct phases: a rough programming phase that quickly programs data to an initial level above a first threshold voltage, and a fine programming phase that precisely programs data to the target level. This segmentation allows the system to achieve both high storage capacity and measurement precision by separating the coarse positioning and fine adjustment operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The rough programming phase is performed as a preliminary action before the fine programming phase. By first programming all data to an initial level above the first threshold voltage, the system prepares the memory cells for subsequent precise programming to target levels, reducing the complexity and improving the accuracy of the final programming operation.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If multiple buffers are used to support multi-level programming algorithm, then programming accuracy improves, but device complexity increases

Engineering Contradiction:
Improveprogramming accuracyVSAvoidnumber of buffers
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

A single buffer is designed to perform multiple functions: it serves as both the data buffer for holding programming data and the verify buffer for storing verification results. This multi-functional buffer design eliminates the need for separate buffers, reducing device complexity while maintaining programming accuracy through the two-phase programming algorithm.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the data buffer and verify buffer into a single buffer structure. By combining these two previously separate components, the system reduces the total number of buffers required, simplifying the device architecture while still supporting the multi-level programming algorithm that requires both data storage and verification capabilities.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If two-phase programming is implemented to improve programming uniformity, then programming accuracy improves, but loss of time increases due to additional programming phases

Engineering Contradiction:
Improveprogramming uniformityVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The programming operation is structured as periodic action with two distinct phases: rough programming followed by fine programming. Each phase uses appropriate pulse characteristics (stronger pulses for rough programming, weaker pulses for fine programming) to achieve uniform programming across all cells while minimizing total programming time through optimized phase transitions.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7924628B2Operation of a non-volatile memory array
Publication Date: 2011.04.12 SPANSION ISRAEL LTD
  • US7924628B2 patent drawing
  • US7924628B2 patent drawing
  • US7924628B2 patent drawing

AI summary

A cache programming operation which requires 2 SRAMs (one for the user and one for the array) may be combined with a multi-level cell (MLC) programming operation which also requires 2 SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs (or buffers). One of the buffers (User SRAM) receives and stores user data. The other of the two buffers (Cache SRAM) may perform a caching function as well as a verify function. In this manner, if a program operation fails, the user can have its original data back so that he can try to reprogram it to a different place (address).