Flash Memory Layout Area Reduction via Common Active Region
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Solution Overview
Problem
The increasing integration of semiconductor memory devices, particularly flash memory devices, results in reduced pattern size and spacing, limiting the horizontal width and increasing the vertical layout length of the data transmission block, leading to a larger layout area.
Innovation Solution
The implementation of a flash memory device with a data transmission block that includes power and select connection portions, where even and odd bit lines are connected to common bit lines via transistors, and these transistors are formed in a common active region, reducing the vertical layout length and overall layout area by sharing active regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If double patterning technology is applied to reduce pattern size and spacing, then integration degree increases, but horizontal width is limited and vertical layout length increases
Solution Approach 1:
The patent reconfigures the data transmission block layout by introducing a common active region that accommodates both power connection portions and select connection portions. This dimensional reorganization allows transistors to be arranged in a shared space rather than sequentially along the vertical axis, effectively converting a one-dimensional vertical stacking problem into a two-dimensional planar arrangement that reduces overall vertical footprint.
Solution Approach 2:
The patent merges the previously separate power connection portions and select connection portions into a single common active region. By combining these functional blocks that were traditionally laid out separately, the design eliminates redundant vertical spacing and insulation regions, achieving compact integration while maintaining all necessary electrical connections for bit line pairs.
2Ease of manufacture
If separate active regions are used for power and select connection portions, then functional separation is achieved, but layout area increases
Solution Approach 1:
The patent combines power connection portions and select connection portions within a single common active region, eliminating the need for separate active regions while maintaining distinct functional connectivity. This merging approach reduces layout area by removing redundant insulation regions and optimizing transistor placement in the shared space.
Solution Approach 2:
Within the common active region, the patent applies local quality by providing different connection configurations for even and odd bit lines. Even bit lines connect to common bit lines through even select transistors, while odd bit lines connect through odd select transistors, with each having dedicated power transistors. This localized differentiation maintains functional separation needs while achieving overall area reduction.
Data Source
AI summary
A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.