Memory Chip Input Buffer Control via Address Final-Cycle Signal
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Solution Overview
Problem
In multi-chip SSDs, non-target NAND chips consume unnecessary power when their input buffers are activated with a delay during data writing, potentially leading to data loss due to the activation of input buffers after receiving the address of the writing destination.
Innovation Solution
The input buffer is kept active during the data load cycle by using an address final-cycle signal to ensure timely activation, regardless of whether the NAND chip is the access target, reducing power consumption and preventing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the input buffer is activated with a delay after receiving the address of the writing destination, then power consumption is reduced for non-target chips, but data loss occurs due to delayed activation
Solution Approach 1:
The input buffer is activated in advance during the address final cycle, before the actual data writing begins. This preliminary activation ensures that the buffer is ready to receive data immediately when the write operation starts, preventing data loss while avoiding continuous activation for non-target chips.
Solution Approach 2:
The input buffer activation state is dynamically controlled based on the address final cycle signal. The buffer transitions from inactive to active state at the appropriate timing determined by the address cycle completion, allowing adaptive power management that responds to actual operational needs rather than maintaining a fixed state.
2Reliability
If the input buffer is kept active continuously, then data loss is prevented, but power is wasted on non-target chips
Solution Approach 1:
The input buffer is activated periodically only during the address final cycle of each write operation, rather than remaining continuously active. This periodic activation pattern ensures data integrity is maintained when needed while minimizing power consumption during idle periods for non-target chips.
Solution Approach 2:
Different activation timing is applied to different chips based on whether they are target or non-target chips. Target chips activate their input buffers during the address final cycle, while non-target chips keep them inactive, creating localized quality differences in buffer activation states across the multi-chip system.
3Device complexity
If multiple NAND chips share common signal lines, then device complexity is reduced, but signal collision occurs during simultaneous access
Solution Approach 1:
The system preliminarily determines which chip is the access target by comparing higher-order address bits with option pin settings before data transmission begins. This preliminary identification allows the system to prepare the correct chip's input buffer for reception while keeping other chips' buffers inactive, preventing signal collision on shared lines.
Solution Approach 2:
The chip selection mechanism uses feedback from address comparison between the control chip and option pin settings to determine which NAND chip should be active. This feedback loop ensures that only the intended target chip activates its input buffer, maintaining signal integrity on shared communication lines.
Data Source
AI summary
A memory chip includes: a memory region; a chip determining unit configured to perform a chip determination, in writing operation, to determine whether or not the memory region is a writing target on the basis of an inputted address of writing destination, and to output a determination result of the chip determination; an address-cycle identifying unit configured to detect a final cycle of the address of writing destination, and to output a detection result at a timing before the output of the determination result; and a buffer controller configured to switch an input buffer from one state to another on the basis of the determination result, wherein the buffer controller keeps the input buffer in an active state irrespective of the determination result of the chip determination while the address-cycle identifying unit is outputting the detection result.