Nonvolatile Memory Stepwise Gate Voltage Writing
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices using Channel Hot Electron (CHE) technology face limitations in write current capacity, leading to restricted parallel write operations and extended write times due to the current drive performance of the power supply circuit, which increases chip area and circuit complexity when attempting to enhance write performance.
Innovation Solution
A nonvolatile semiconductor memory device and method that selectively apply a gate voltage in multiple steps to reach a target threshold voltage for each memory cell, allowing for parallel writing of data across multiple cells without verification between steps, thereby reducing the required write current and enhancing write efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the power supply circuit is enhanced to increase write current capacity for parallel write operations, then write performance is improved, but chip area and circuit complexity increase
Solution Approach 1:
The write operation is segmented into multiple stages with progressively increasing gate voltages. Instead of applying the full write voltage simultaneously to all selected memory cells, the patent divides the write process into sequential voltage steps (e.g., Vpgm1, Vpgm2, Vpgm3), where each stage writes to a subset of cells. This segmentation reduces the peak current demand on the power supply circuit while maintaining the ability to perform parallel writes across the entire array.
Solution Approach 2:
The patent dynamically adjusts the gate voltage applied to selected memory cells based on their individual write status. The write circuit selectively applies different voltage levels to different groups of cells during the write process, transitioning from lower voltages to higher voltages in subsequent stages. This dynamic voltage adjustment optimizes current utilization and reduces the overall current burden on the power supply circuit.
2Productivity
If the power supply circuit is enhanced to increase write current capacity, then parallel write capability is improved, but chip area increases
Solution Approach 1:
The memory cell array is divided into multiple groups that are written in sequential stages. Each group receives the full write voltage at different time intervals rather than simultaneously. This segmentation allows the use of a smaller, more compact power supply circuit that can deliver the required current in staggered pulses rather than requiring a large circuit capable of delivering all current simultaneously.
Solution Approach 2:
The write operation employs periodic action by cycling through different groups of memory cells in successive time periods. Each period involves applying the write voltage to a specific group, then transitioning to the next group. This periodic approach enables parallel writes across the entire array using a compact power supply that operates at full capacity in each period rather than requiring reduced capacity continuous operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables simultaneous writing to multiple memory cells with reduced write time and chip area, while maintaining stable write current performance, by dividing the write operation into stages with progressively increasing gate voltage, allowing for efficient data writing without increasing the power supply circuit's complexity.
Implementation Method 1
A nonvolatile semiconductor memory device is known, such as a flash memory of an NOR type in which flash memory cells using CHE (Channel Hot Electron) are arranged in a matrix
Data Source
AI summary
In a nonvolatile semiconductor memory device, a memory cell array has a plurality of nonvolatile memory cells arranged in a matrix. A selecting section selects as selection memory cells, at least two of the plurality of nonvolatile memory cells from the memory cell array. A write section applies to the selection memory cells, a gate voltage which increases step by step, until a threshold voltage of each of the selection memory cells reaches a target threshold voltage, such that the threshold voltage increases step-by-step.