Memory Device Bit Line Precharge Timing for ISPP Efficiency
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Solution Overview
Problem
Memory devices face efficiency decreases due to channel boosting during program operations using the incremental step pulse program (ISPP) scheme, which affects the reliability and speed of programming.
Innovation Solution
A memory device and its operating method that include a control circuit and page buffers to manage bit line precharging and voltage application, allowing for incremental step pulse programming by selectively connecting bit lines to power or ground based on logic levels, optimizing the precharge timing and voltage application across multiple program loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit line precharge operation is performed from fourth time point to second time point during first program loop, then channel boosting is prevented, but programming time increases
Solution Approach 1:
The bit line precharge operation is performed in advance from the fourth time point (before first time point) to the second time point during the first program loop. This preliminary action prepares the bit lines before the pass voltage is applied to word lines, preventing channel boosting effects that would otherwise occur during subsequent programming operations.
Solution Approach 2:
The patent implements dynamic adjustment of precharge timing across different program loops. During the first program loop, precharge occurs from fourth time point to second time point, while during remaining program loops, precharge occurs from fourth time point to fifth time point (same as or ahead of first time point). This dynamic timing adjustment optimizes both reliability and programming speed.
2Stability of the object's composition
If pass voltage is applied to all word lines from first time point to second time point, then programming uniformity is improved, but channel boosting occurs reducing efficiency
Solution Approach 1:
The bit line precharge operation is performed before the pass voltage is applied to word lines (from fourth time point to second time point during first loop). This preliminary preparation of bit lines ensures uniform programming conditions are established before the actual programming phase, preventing channel boosting while maintaining programming uniformity.
Solution Approach 2:
The patent changes the timing parameters of bit line precharge operation across different program loops. By adjusting when the precharge operation occurs relative to the pass voltage application, the patent optimizes both programming uniformity and efficiency, preventing channel boosting effects.
3Productivity
If bit line precharge operation timing is adjusted to fifth time point in remaining program loops, then program efficiency is maintained, but control complexity increases
Solution Approach 1:
The control circuit dynamically adjusts the bit line precharge operation timing based on the program loop number. During the first program loop, precharge occurs from fourth time point to second time point, while during remaining program loops, precharge occurs from fourth time point to fifth time point. This dynamic control maintains program efficiency while managing complexity through systematic timing differentiation.
Data Source
AI summary
A memory device comprises a memory cell array and a control circuit. The control circuit applies a pass voltage to each of a selected and unselected word line from a first to second time point whenever a program loop is performed once. Then, the control circuit applies a program voltage to the selected word line and the pass voltage to the unselected word line from the second to third time point, performs a bit line precharge operation from a fourth time point ahead of the first time point to the second time point when a first program loop is performed, and performs the bit line precharge operation from the fourth time point to a fifth time point, which is the same as or ahead of the first time point, when the other program loops are performed.